timing_error_for_pll_afi_clock_on_ddr3_ip_controller

The setup violations showed in the report are all asynchronous path. You can use 'set clock group' constraint to eliminate the relationship between 'inst|ddr3|pll0|pll_dq_write_clk ' and 'dqs_n[3]_OUT'.

You don't need to constraint all the clocks, just apply it to the clocks of asynchronous path( the launch and latch clock ).

BTW you can try to apply the following constraint:

'derive_pll_clocks'

You mean the same violation still exits? Could you show the violation in the timing analyzer which is better to view.

BTW why you put the altera_reserved_tck in the group? I think you don't need to constraint it.

There are also synchronization path violation. Could you please provide your project for further analysis.

Hi there, I can't open timing analyzer with the project you provided. Could you provide the project which has completed the compilation process?

Please provide all the files of the project, and you can exclude you RTL(.v file) for confidentiality.

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Try reduce the number of logic levels to 2-3 by adding pipeline register (this will add latency in your design).

As higher logic level will increase delay on the critical path.

You may checkout this video on @16.49 minute marks

https://www.youtube.com/watch?v=UGGkKZylJBo

Regards,

Richard Tan

Do you able to close timing?

Regards,

Richard Tan

Hi there, what violation you get, could you please share the path in timing analyzer.

Could you please provide your project (.qar) for investigation. You can remove all RTL files for confidentiality.

Thanks a lot.