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SERMASWATHIKA's avatar
SERMASWATHIKA
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1 year ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
RichardT_altera's avatar
RichardT_altera
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1 year ago

Do you able to close timing?


Regards,

Richard Tan


  • SERMASWATHIKA's avatar
    SERMASWATHIKA
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    1 year ago

    Hi,

    No still i am working on it..but for me timing violations are showing within the ip files. i cant modify the rtl path , so need assistance for this.