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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
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TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

The setup violations showed in the report are all asynchronous path. You can use 'set clock group' constraint to eliminate the relationship between 'inst|ddr3|pll0|pll_dq_write_clk ' and 'dqs_n[3]_OUT'.


SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

Hi Ting,

I have added constraint for the clocks like you have mentioned, but still facing the timing violation error:

could you please give suggestions whether this constraints are okay?