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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

You mean the same violation still exits? Could you show the violation in the timing analyzer which is better to view.

BTW why you put the altera_reserved_tck in the group? I think you don't need to constraint it.


SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

Hi,

for better view, i have attached the screenshot of violation