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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

Hi there, I can't open timing analyzer with the project you provided. Could you provide the project which has completed the compilation process?

Please provide all the files of the project, and you can exclude you RTL(.v file) for confidentiality.

  • SERMASWATHIKA's avatar
    SERMASWATHIKA
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    2 years ago

    ok , i will send the project files which is compiled within today