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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
RichardT_altera's avatar
RichardT_altera
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2 years ago

Try reduce the number of logic levels to 2-3 by adding pipeline register (this will add latency in your design).

As higher logic level will increase delay on the critical path.

You may checkout this video on @16.49 minute marks

https://www.youtube.com/watch?v=UGGkKZylJBo

Regards,

Richard Tan

  • SERMASWATHIKA's avatar
    SERMASWATHIKA
    Icon for Contributor rankContributor
    2 years ago

    ok i will check this and let you know