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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

You don't need to constraint all the clocks, just apply it to the clocks of asynchronous path( the launch and latch clock ).

BTW you can try to apply the following constraint:

'derive_pll_clocks'


  • SERMASWATHIKA's avatar
    SERMASWATHIKA
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    2 years ago

    Hi ,

    I have tried with derive_pll_clock also. but still facing timing violation issue.

    do i miss anything?