Forum Discussion
SERMASWATHIKA
Contributor
Contributortiming_error_for_pll_afi_clock_on_ddr3_ip_controller
Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
TingJiangT_IntelContributor
ContributorThere are also synchronization path violation. Could you please provide your project for further analysis.
SERMASWATHIKAContributor
ContributorHi,
i have attached the project archive with this response. Please let me know if you have any query on this. please give solution for this violation
