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JuanEscobedo's avatar
JuanEscobedo
Icon for New Contributor rankNew Contributor
3 months ago

Unable to simulate DDR3 controller

Hello,

I have a design with DDR3 and I am using the Altera DDR3 SDRAM Controller with UniPHY for Intel FPGA IP to interface with it and I want to run a simulation that involves the controller and the actual DDR3 memory model. I have never had to run a simulation involving an external DDR memory so I want to start by running a simulation of the example design for the IP.

When configuring the IP, at the end, I enable the "Generate Example Design" and I see the respective folders _sim and _example_design created. This completes without errors.

Inside the _example_design folder, there are two additional ones: example_project and simulation. Inside the exaple_project folder, I see a QPF file. I can open that from Quartus as "Open Project".

However, after clicking "Analysis and Synthesis" and double clicking on the top level module, I get this error:

Trying to run Tools-> RTL Simulation doesn't give any errors but Questa never launches.

I am using Quartus 23.1 on a Windows 11 machine.

Any help would be appreciated.

Juan Escobedo, Ph.D.

Memory

7 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi Juan Escobedo,


    I believe the generated example design doesn't generate .qsys file and .ip file but it's generated the modules in .v or .sv or .vhdl.

    Therefore, when you are clicking on top level file, it will show invalid Platform Designer file because no .qsys file is available.

    You can goto the file by right click --> locate node --> locate in design file.


    If you want to run the simulation, you can follow these steps:

    1. Open the Questasim simulator.
    2. Change the directory to *_example_design\simulation\<verilog or vhdl>\mentor
    3. run command "do run.do" in Questa command prompt.

    Link for reference: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/simulating-the-example-design.html


    Regards,

    Adzim


    • JuanEscobedo's avatar
      JuanEscobedo
      Icon for New Contributor rankNew Contributor
      3 months ago

      Hello Adzim,

      I changed directory but the run.do file seems to be missing:
      do run.do
      # ** Error: The msim_setup.tcl script does not exist. Please generate the example design RTL and simulation scripts. See ../../README.txt for help.
      # Error in macro ./run.do line 11
      # The msim_setup.tcl script does not exist. Please generate the example design RTL and simulation scripts. See ../../README.txt for help.
      # while executing
      # "error "The msim_setup.tcl script does not exist. Please generate the example design RTL and simulation scripts. See ../../README.txt for help.""
      # invoked from within
      # "if {[file exists msim_setup.tcl]} {
      # source msim_setup.tcl
      # dev_com
      # com
      # # the "elab_debug" macro avoids optimizations which preserves signals so tha..."

  • PalmPlumb's avatar
    PalmPlumb
    Icon for New Contributor rankNew Contributor
    3 months ago

    Hi Adzim,

    Thank you for the detailed explanation. It makes sense that the invalid Platform Designer file error occurs due to the absence of a .qsys file. The workaround to locate the design file via right-click is helpful. For the simulation steps, I’ll try following your instructions with Questasim and see if the "do run.do" command works as expected. The reference link should also be useful for further clarification. Appreciate your assistance!

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi Juan,


    It's seemed the simulation script is not yet generated.

    If you navigate to *example_design\simulation\ path, you will see the README.txt file.

    The README.txt has some instruction on how you can generate the simulation example design.

    Please let me know if you still facing the error after generating the design.


    Regards,

    Adzim


    • JuanEscobedo's avatar
      JuanEscobedo
      Icon for New Contributor rankNew Contributor
      3 months ago

      Hello Adzim,

      I followed the instructions on the README and I was able to run the simulation.

      However, before I close the post, I have 2 questions:

      1) In the simulation, I see the following modules

      But I was expecting to see these from the example design:

      Particularly d0 was of interest since it generates the Avalon bus signals.
      Am I missing something here or am I running the wrong simulation?

      2) Are there instructions on how would I migrate what I need from the example design to simulate my actual design but including the external memory?

      Thanks beforehand,

      Juan

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi Juan,


    You can add the e0 instance in the Wave windows before run the simulation if you like to see the avalon interface and other signal. You should be running correct simulation at this point.


    The simulation doesn't have hardware, thus it's create a module to represent the hardware in order to simulate the signal, IP, etc.

    Therefore, the instances in simulation may a bit different from the Quartus design.

    You need to check the instance for the object that you need to simulate.


    I'm not sure if there is any instruction to migrate the design. I think we don't provide that.

    You need to manually add the files into your design.


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi Juan,


    FYI, the Intel community will freeze in next 2 weeks for updating the support system for Altera. Meaning you can only read the content but cannot edit or reply in the thread.

    I also will OOO next week. Thus, I think it's better to close this thread for now.


    I think your questions have been addressed. I will transition this thread to community support.

    In next month, you can open a new thread to continue the discussion.

    Thank you for your understanding.


    Regards,

    Adzim