Forum Discussion
JuanEscobedo
New Contributor
New ContributorUnable to simulate DDR3 controller
Hello, I have a design with DDR3 and I am using the Altera DDR3 SDRAM Controller with UniPHY for Intel FPGA IP to interface with it and I want to run a simulation that involves the controller and t...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Juan,
You can add the e0 instance in the Wave windows before run the simulation if you like to see the avalon interface and other signal. You should be running correct simulation at this point.
The simulation doesn't have hardware, thus it's create a module to represent the hardware in order to simulate the signal, IP, etc.
Therefore, the instances in simulation may a bit different from the Quartus design.
You need to check the instance for the object that you need to simulate.
I'm not sure if there is any instruction to migrate the design. I think we don't provide that.
You need to manually add the files into your design.
Regards,
Adzim
