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JuanEscobedo's avatar
JuanEscobedo
Icon for New Contributor rankNew Contributor
3 months ago

Unable to simulate DDR3 controller

Hello, I have a design with DDR3 and I am using the Altera DDR3 SDRAM Controller with UniPHY for Intel FPGA IP to interface with it and I want to run a simulation that involves the controller and t...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi Juan,


It's seemed the simulation script is not yet generated.

If you navigate to *example_design\simulation\ path, you will see the README.txt file.

The README.txt has some instruction on how you can generate the simulation example design.

Please let me know if you still facing the error after generating the design.


Regards,

Adzim


JuanEscobedo's avatar
JuanEscobedo
Icon for New Contributor rankNew Contributor
3 months ago

Hello Adzim,

I followed the instructions on the README and I was able to run the simulation.

However, before I close the post, I have 2 questions:

1) In the simulation, I see the following modules

But I was expecting to see these from the example design:

Particularly d0 was of interest since it generates the Avalon bus signals.
Am I missing something here or am I running the wrong simulation?

2) Are there instructions on how would I migrate what I need from the example design to simulate my actual design but including the external memory?

Thanks beforehand,

Juan