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JuanEscobedo's avatar
JuanEscobedo
Icon for New Contributor rankNew Contributor
3 months ago

Unable to simulate DDR3 controller

Hello, I have a design with DDR3 and I am using the Altera DDR3 SDRAM Controller with UniPHY for Intel FPGA IP to interface with it and I want to run a simulation that involves the controller and t...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi Juan Escobedo,


I believe the generated example design doesn't generate .qsys file and .ip file but it's generated the modules in .v or .sv or .vhdl.

Therefore, when you are clicking on top level file, it will show invalid Platform Designer file because no .qsys file is available.

You can goto the file by right click --> locate node --> locate in design file.


If you want to run the simulation, you can follow these steps:

  1. Open the Questasim simulator.
  2. Change the directory to *_example_design\simulation\<verilog or vhdl>\mentor
  3. run command "do run.do" in Questa command prompt.

Link for reference: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/simulating-the-example-design.html


Regards,

Adzim


JuanEscobedo's avatar
JuanEscobedo
Icon for New Contributor rankNew Contributor
3 months ago

Hello Adzim,

I changed directory but the run.do file seems to be missing:
do run.do
# ** Error: The msim_setup.tcl script does not exist. Please generate the example design RTL and simulation scripts. See ../../README.txt for help.
# Error in macro ./run.do line 11
# The msim_setup.tcl script does not exist. Please generate the example design RTL and simulation scripts. See ../../README.txt for help.
# while executing
# "error "The msim_setup.tcl script does not exist. Please generate the example design RTL and simulation scripts. See ../../README.txt for help.""
# invoked from within
# "if {[file exists msim_setup.tcl]} {
# source msim_setup.tcl
# dev_com
# com
# # the "elab_debug" macro avoids optimizations which preserves signals so tha..."