Forum Discussion
JuanEscobedo
New Contributor
New ContributorUnable to simulate DDR3 controller
Hello, I have a design with DDR3 and I am using the Altera DDR3 SDRAM Controller with UniPHY for Intel FPGA IP to interface with it and I want to run a simulation that involves the controller and t...
PalmPlumbNew Contributor
New ContributorHi Adzim,
Thank you for the detailed explanation. It makes sense that the invalid Platform Designer file error occurs due to the absence of a .qsys file. The workaround to locate the design file via right-click is helpful. For the simulation steps, I’ll try following your instructions with Questasim and see if the "do run.do" command works as expected. The reference link should also be useful for further clarification. Appreciate your assistance!
