Forum Discussion
wangduoyu
New Contributor
New ContributorAgilex 5: Connecting multiple AXI Masters to DDR without explicit Interconnect IP
Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply conn...
wangduoyuNew Contributor
New ContributorThanks. Is it necessary to use an AXI Bridge to solve the addressing issue?
AdzimZM_Altera
Regular Contributor
Regular ContributorHello wangduoyu,
For the address out of range issue, you can try to modify the module or add Address Span Extender IP to resolve the issue.
I think AXI Bridge may be used for utilize the resource of the manager and subordinate interface.
- Address Span Extender IP: https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1-1/address-span-extender.html
- AXI Bridge: https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1-1/axi-bridge.html
Regards,
Adzim
