Can't find Agilex 7 M I/O PLL Reconfiguration Design Example
Hi, Recently updated document "Agilex™ 7 Clocking and PLL User Guide M-Series", 769001 2025.10.09 refers to a design example which uses an EMIF Calibration IP for I/O PLL reconfiguration: 6.1.7. Design Example for I/O PLL Reconfiguration I can't find this design on Intel or Altera sites. Can anyone please tell if it exists. I can find very similar Agilex 7 PLL reconfig examples but they use different calibration IP, not usable with Agilex 7M devices. I'm trying to utilize IOPLL's dynamic output phase adjustment only. This was easy with earlier generation devices as the I/O PLL provided a specific control interface for this purpose. Phase shift control port or something similar. Thanks, Ju-ti
MSGDMA: Is Linux Driver Mandatory? Using devmem2 & F2SDRAM Bridge
Hello everyone, I am currently working on an MSGDMA implementation. I have verified that I can read the MSGDMA CSR and Descriptor registers via the LWH2F bridge using devmem2. My setup is configured in Streaming-to-Memory-Mapped (ST-to-MM) mode. I have two specific questions regarding this setup: 1、Is configuring the MSGDMA Linux kernel driver a mandatory condition for the hardware to function correctly? Is it possible to bypass the driver and configure the MSGDMA to start data transfer directly using devmem2 (user-space access)? 2、I noticed that some implementations write to the PS-side memory via the FPGA-to-HPS bridge. However, my design utilizes the F2SDRAM link, as indicated by the numbered sequence in the attached diagram. Could you please confirm if this architectural approach is feasible?
Memory Mapped Interconnect Reset Net Polarity Conflict
I have developed a simple client Avalon Memory Mapped Interface custom IP block. The MM interconnect block automatically generated a width adapter component that is causing an LNT-30023 - Reset Nets with Polarity Conflict DRC. It is not affecting the functionality of my custom MM block, but I am still interested in understanding the root cause of this issue. Details to follow, thank you in advance for any help. Custom Avalon Memory Mapped Interface consists of the following signals: clk reset_n [7:0] writedata write [7:0] address Various conduit signals The master is the JTAG to Avalon Master Bridge which defaults to have 32bit address and writedata signals. For this configuration a merlin width adapter is automatically generated in the mm_interconnect block of the platform system designer. Both the custom IP block and the JTAG to Avalon Master Bridge are connected to an low-assert (reset_n) Reset Bridge IP Block. The custom IP block is configured to be an low-assert reset. I was under the impression all generated MM interconnect IP would inherit the low-assert reset. Instead my Design Assistant Summary declares the following DRC error: LNT-30023 - Reset Nets with Polarity Conflict. The detailed description is as follows, where <my_block> is a placeholder for my custom block name: Driver: u0|mm_interconnect_0|<my_block>_avalon_slave_0_cmd_width_adapter|use_reg Non-inverted signal: u0|mm_interconnect_0|<my_block>_avalon_slave_0_cmd_width_adapter|data_reg[16]|SCLR Inverted Signal: u0|mm_interconnect_0|<my_block>_avalon_slave_0_cmd_width_adapter|address_reg[1]|SCLRAgilex 5: Connecting multiple AXI Masters to DDR without explicit Interconnect IP
Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply connect two AXI masters directly to the single DDR AXI slave port (as shown below)? Will the interconnect fabric generate the necessary arbitration and routing logic in this case？
Error: dut.p0_hip_status has no associated reset.
Hello Altera I am using Quartus Prime Pro 25.1.0 build 129 03/26/2025 SC Pro Edition. In my Agiliex 7 Design project, I have Intel R-Tile MCDMA for PCI Express intel_pcie_rtile_mcdma Version 5.3.1 Ip instantiated as "dut". in parameters settings I have enabled to have hip status interface. https://www.intel.com/content/www/us/en/docs/programmable/683821/25-1-1/hard-ip-status-interface.html this interface is connected to a custom design QCP file. The QCP uses "app_clk" and "app_nreset_status" from dut ip as its clk and reset inputs. They go through clock bridge and reset bridge. Clock and reset outputs from these bridges are used internally in custom logic code. In platform designer as I connect "dut.p0_hip_status" and "custom_module.pcie_ep_hip_status_in" ports, I get an error as following "Error: pcie_ed: Interfaces custom_module.pcie_ep_hip_status_in and dut.p0_hip_status must have matching associated resets, but dut.p0_hip_status has no associated reset." This Error does not make sense to me, as dut`s hip status interface and my qcp`s status interface ports shows correct clock and reset association in component instantiation tab; and my custom design uses same clock and reset to its clock and reset bridge inputs. can you please help me to understand what is this error about and how do i resolve it?
ALT PLL GUI MESSDED UP ON INVOCATION
Hi All ALTERA Experts, I have a problem setting up a new PLL due to the GUI looking like the mess you can see in my attached screenshot. I am using Quartus Standard edition Version 25.1 I am on a windows 10 machine and all of the other IP GUIs seem to work fine, its just this PLL IP GUI that seems to get messed up. I am using a MAX10 FPGA. Both my PC and Graphics card are working fine. Can anybody suggest why this occurs ? Thanks, Barryp0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express
Hi, I'm using GTS AXI Streaming intel FPGA IP for PCI Express to implement PCIe on Agilex 5 FPGA (A5ED065BB32AE4 ,Quartus Prime 25.1) . I connect Pin p0_pin_perst_n_i to a 3.3v pll up resistance on the board while pin p0_pin_perst_n_1_i is left floating . When testing on the board , p0_pin_perst_n remains asserted and the p0_reset_status_n remains low . It seems like the IP cannot jump out off reset . I wonder what may cause this situation and how can i solve the problem . I also tried to simulate the ip in Questa intel FPGA . I found that p0_pin_perst_n deasserted correctly after system PLL got locked in simulation .The simulation and the on board testing i made were using the same top module .Here is my testing project . Many thanks, Chester
onnecting the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP
Hello Intel forums, I'm trying to connect a out_coreclk from an F-tile Reference and System PLL Clock IP to an IOPLL. I understand that I cannot do this directly, so I'm following the workaround described here: https://www.intel.com/content/www/us/en/support/programmable/articles/000098971.html Here is my code: clocko_blocko : block signal half_core : std_logic; component clk_ctrl is port ( inclk : in std_logic := 'X'; -- clk clock_div1x : out std_logic -- clk ); end component clk_ctrl; component pll is port ( refclk : in std_logic := 'X'; -- clk locked : out std_logic; -- export rst : in std_logic := 'X'; -- reset outclk_0 : out std_logic -- clk ); end component pll; signal half_core_iopll_ref : std_logic; signal source : std_logic; begin proc_halver : process(coreclk_feb) begin if rising_edge(coreclk_feb) then half_core <= not half_core; end if; end process proc_halver; clctrl : component clk_ctrl port map ( inclk => half_core, clock_div1x => half_core_iopll_ref ); ipll : component pll port map ( refclk => half_core_iopll_ref, locked => open, rst => rst, outclk_0 => clk_320 ); end block clocko_blocko; Unfortunately. the pll never locks. Using a firmware module, I've measured the frequency of "coreclk_feb", "half_core", and "half_core_iopll_ref" and they all have correct values, but "clk_320" has a nonsensical value. Are there particular settings needed for the Clock Control FPGA IP buffer and IOPLL FPGA IP that are not covered in the linked post? My IOPLL is set to double the input frequency to compensate for the division in the "proc_halver" process, is that a problem? I've tried this in Quartus 23.4 and 24.3.1 Cheers, Sam
