SerialLite II license for Arria10 FPGA
I purchased a SerialLite II license and received the license file. However, I need a special license to support Arria 10 FPGAs. In previous years, I obtained this license by contacting Altera technical support through a sales representative. This year, I was advised to contact Altera through the forum. Please help me find the correct way to obtain the necessary license file.
AI Suite Docker Update?
Hello Community, I see the 2026.1.1 version of the AI Suite is available - https://www.altera.com/downloads/add-development-tools/fpga-ai-suite-version-2026-1-1 Is there an expected delay or expected date for the Docker to reflect this version? - https://hub.docker.com/r/alterafpga/fpgaaisuite Thank you,
Avalon Transaction Responses & Bridges
Hello I have a question about the behavior of Avalon-MM Pipeline Bridges concerning the response signals. I have the following setup: 2 (or more) Avalon-MM Masters Master cmd_ctrl (supports Avalon responses) Master B (no response support) global_mm_bridge (pipeline Bridge IP Core) with Support for Transaction Responses Multiple Slaves Slave global_reg (simple register read & write access) other Slaves do not have Avalon response signals (neither readdatavalid, nor writeresponsevalid) My understanding of Avalon-MM bridges was always that they act as kind of "transparent bridge", i.e. they do not sent responses by themselves, but only transfer/route the responses of the addressed slave behind the bridge. However, when I capture the transactions using Signaltap I noticed that the Bridge is creating a writerepsonse valid before, this is even processed by the addressed slave. In the signaltap capture, you can see the writereponse (highlighted in yellow) arriving at the initiating master (cmd_ctrl) before, the addressed slave (global_reg) even generates it. Hence I would assume this is generated by the mm_bridge directly after it accepts the write command. Now my questions are: Is this the intended behavior of a pipeline bridge? If yes, is there any way to modify the settings of the bridge, to make sure the master (cmd_ctrl) only receives a writeresponsevalid after the respective slave has sent it? Background is: cmd_ctrl also needs to write/read from slave B, however this must not be done, before the slave global_reg has fully processed the write command, as it must prepare some glue logic. Is there any other option to realize a fully transparent Avalon-MM bridge? best regards Fabiantennm_mac in m18x18_sumof2 mode on Agilex 7 - spurious systolic register inserted in Quartus 25.3
Device: Intel Agilex 7 Quartus version: Quartus Prime Version 25.3.0 Build 109 09/24/2025 SC Pro Edition Atom: tennm_mac Mode: m18x18_sumof2 with pre-adder (operand_source_may = "preadder") Description I am directly instantiating tennm_mac atoms in m18x18_sumof2 mode for a high-throughput multiplications. The design uses the pre-adder on both multipliers (az/bz ports) and has all four pipeline stages enabled (ax_clken, input_pipeline_clken, second_pipeline_clken, output_clken all set to "0"). I observe incorrect result at the output of the multiplier. Inspecting the Resource Property Viewer confirms that systolic registers have been placed on the A* path inside the DSP block, even though: input_systolic_clken is explicitly set to "no_reg" Systolic mode is not selected — the operation mode is m18x18_sumof2 The systolic register is architecturally present only on the A* datapath; the B* datapath has no equivalent register, so the skew is asymmetric by design. The result is incorrect sum of multiplies output on hardware - the coefficient and data samples presented to the multiplier are misaligned by one clock cycle. Minimal defparam set that reproduces the issue: tennm_mac u_mac ( .ax(ax), .ay(ay), .az(az), .bx(bx), .by(by), .bz(bz), .clk(clk), .ena(3'b111), .clr(2'b00), .resulta(result) ); defparam u_mac.operation_mode = "m18x18_sumof2", u_mac.operand_source_may = "preadder", u_mac.operand_source_mby = "preadder", u_mac.ax_clken = "0", u_mac.bx_clken = "0", u_mac.ay_scan_in_clken = "0", u_mac.by_clken = "0", u_mac.az_clken = "0", u_mac.bz_clken = "0", u_mac.input_pipeline_clken = "0", u_mac.second_pipeline_clken = "0", u_mac.output_clken = "0", u_mac.input_systolic_clken = "no_reg", // <-- ignored u_mac.clear_type = "none"; Questions Are my assumptions that systolic registers are placed incorrectly correct? Is this a known issue in Quartus 25.3 / with Agilex 7 devices? Similar design compiled correctly on Quartus 17.1 for Arria 10. Any guidance to resolve this issue would be appreciated.
Connecting Intel Agilex FPGA to DE1-SoC via Hub
Hello, I have an Intel Agilex FPGA with QSFP-DD 10 GbE PHY, a DE1-SoC board with 1 GbE PHY, and an Ethernet Hub 1 GbE. I want to connect the Agilex to the DE1-SoC through this hub. I understand the DE1-SoC only supports 1 GbE while the Agilex PHY is capable of 10 GbE. I would like to know the best way to communicate between these boards. Is it possible to configure the Agilex Ethernet IP and PHY to 1 GbE so it can communicate directly through the hub without a physical adapter? If not, would a media converter or adapter be needed to downspeed from 10 GbE to 1 GbE? Are there any recommended best practices for connecting an Agilex to a slower device like the DE1-SoC via Ethernet? Any guidance or experience would be greatly appreciated. Thank you!
Constraints not being picked for DCFIFO
Hi, I am having various DCFIFOs in my design. I have applied constraints according to the ug_fifo. Attaching link for the reference https://faculty-web.msoe.edu/johnsontimoj/EE3921/files3921/ug_fifo.pdf In the DRC report, I am getting a violation of CDC-50007 which shows CDC bus with insufficient constraints and it is showing set_max_skew and set_data_delay are violated. This issue is not coming up for all the DCFIFOs in the design. The violations are there in the path of the delayed_wrptr_g[*] to rs_dgwp|dffpipe*|dffe and rdptr[*] to ws_dgrp[*] |dffpipe*|dffe. In the same DCFIFO, violation is coming only on either wr_ptr or rd_ptr. Could you suggest why this constraint is not being picked in some selected FIFOs and only in either wr / rd paths? set_data_delay is not prescribed as per the ug_fifo.Accessing registers in the PCIE IP beyond MCDMA using system console
Hi, I have compiled the MCDMA IP (R-Tile based) in EP mode. I have a custom controller IP interfaced with MCDMA IP. There is a CSR Lite Interface on the port list which is a master interface. I have a JTAG to Avalon master bridge through which I want to access the registers in the MCDMA as well as the controller beyond the MCDMA. As JTAG is a master interface and the CSR Lite is also a master interface, they can't be interfaced together. Please suggest how can I interface the JTAG master so that I can access the registers inside the controller as well as MCDMA IP. Also is there any way to access the registers inside MCDMA IP without using JTAG to Avalon master bridge?ALT PLL GUI MESSDED UP ON INVOCATION
Hi All ALTERA Experts, I have a problem setting up a new PLL due to the GUI looking like the mess you can see in my attached screenshot. I am using Quartus Standard edition Version 25.1 I am on a windows 10 machine and all of the other IP GUIs seem to work fine, its just this PLL IP GUI that seems to get messed up. I am using a MAX10 FPGA. Both my PC and Graphics card are working fine. Can anybody suggest why this occurs ? Thanks, Barry
