TSUGI
New Contributor
New ContributorWhat is source clock of rx_core_clkout of Serial Lite IV IP
I'm considering to use Serial Lite IV with F-Tile of Agilex 7.
I want to use the recovered clock from Serial Lite IV in the FPGA’s RTL to synchronize with another FPGA.
However, I cannot find a recovered clock port in the port list of the Serial Lite IV User Guide.
Does this IP include a recovered clock port?
My understanding is that the source clock for rx_core_clkout is systempll_refclk.
Hi,
As I understand it, you have some inquiries related to the RX recovered clock port port of the F-Tile Serial Lite IV IP. As I checked the F-Tile Serial Lite IV Intel® FPGA IP User Guide, it seems like there is no RX recovered clock output port supported in this IP. Sorry for the inconvenience.
