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New ContributorWhat is source clock of rx_core_clkout of Serial Lite IV IP
I'm considering to use Serial Lite IV with F-Tile of Agilex 7. I want to use the recovered clock from Serial Lite IV in the FPGA’s RTL to synchronize with another FPGA. However, I cannot find a rec...
Hi,
As I understand it, you have some inquiries related to the RX recovered clock port port of the F-Tile Serial Lite IV IP. As I checked the F-Tile Serial Lite IV Intel® FPGA IP User Guide, it seems like there is no RX recovered clock output port supported in this IP. Sorry for the inconvenience.
