Forum Discussion
Occasional ContributorDE10-Lite and sdram controller ip
Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supported and I find nothing to replace it. The ddram controllers seems to be more complicated and I can’t figure out how to use their in this case. Someone coud help me ?
Thanks
18 Replies
AdzimZM_AlteraRegular Contributor
Hello ETang2,
We're no longer supporting SDRAM Controller IP in current Quartus Standard version.
If you want to use the SDRAM in 25.1, you can try to manually add the verilog code to your project as a custom module.
Regards,
Adzim
SimonTNew Contributor
Hi,
I had the same Issue. For me the Eval Kit was quite useless without that IP core. I found the following temporary "solution" in https://community.altera.com/discussions/ip-and-transceiver/replacement-for-sdram-controller-after-v16-1/52218
Copy the IP core from an Old Quartus ( I think the last version where this core was supported is 18.1) version to the new Quartus version. /ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller
Additionally you need to modify the ip/altera/altera_component.ipx file. You have to add a few additional lines to that file.
</plugin>
<component
name="altera_avalon_new_sdram_controller"
file="sopc_builder_ip/altera_avalon_new_sdram_controller/altera_avalon_new_sdram_controller_hw.tcl"
displayName="SDRAM Controller Intel FPGA IP"
version="20.1"
description=""
tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=false"
categories="Memory Interfaces and Controllers/SDRAM"
factory="TclModuleFactory">
<tag2 key="COMPONENT_EDITABLE" value="false" />
<tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
<tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
<tag2 key="ELABORATION_CALLBACK" value="elaborate" />
<tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
<tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
<tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
<tag2 key="VALIDATION_CALLBACK" value="validate" />
<documentUrl
displayName="User Guide"
type="OTHER"
url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401314928585" />
<documentUrl
displayName="Release Notes"
type="OTHER"
url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
</component>
<plugin
name="altera_avalon_new_sdram_controller.qprs"
file="sopc_builder_ip/altera_avalon_new_sdram_controller/altera_avalon_new_sdram_controller.qprs"
displayName="altera_avalon_new_sdram_controller.qprs"
version="0.0"
description=""
tags=""
categories=""
type="com.altera.sopcmodel.util.IElementPresetList"
subtype=""
factory="PresetFactory">
<tag2 key="PRESET_TYPE" value="altera_avalon_new_sdram_controller" />
</plugin>These entries are taken from the old altera_component.ipx
This worked for me in Quartus 23.1 Lite
- AdzimZM_Altera
Thierry29Hi,
I followed the same procedure to use the "altera_avalon_new_sdram_controller" in a Quartus Lite v25.1 project including a Nios V/m processor for the DE10-Lite board.
The Quartus project including the SDRAM controller compiles correctly. Next the BSP is created followed by the top makefile. The application program is a simple "hello world" (full project attached as an archive - de10_lite_25_1_sdram.zip)
I am encountering a compilation issue when the SDRAM is used. Specifically the problem occurs during the object code linking stage.
1) When only onchip memory is selected in the BSP editor (linker script tab), everything works correctly. Compilation generates an .elf file, and the code executes successfully.
2) When a code section is placed in the SDRAM, the compilation fails. See, for example, the screenshots of BSP editor and Ashling RiscFree IDE: BSP_Onchip_and_SDRAM.png and Errors_Onchip_and_SDRAM.png.
3) When all sections are placed in the SDRAM (except .entry), compilation fails with a slightly different error message. See, for example, the screenshots of BSP editor and Ashling RiscFree IDE: BSP_SDRAM_only.png and Errors_SDRAM_only.png.
The main error message is "helloworld.elf section `.entry' will not fit in region `reset'". Does anyone have an idea what might be wrong in the project and how to resolve this issue?
Thanks a lot for your help.
Thierry
tehjingy_AlteraHi Thierry29
Could you you check if you have untick all the hal.linker option during the BSP Generation?
ETang2Hi AdzimZM_Altera and thanks for the solution that seems to work. I used "System and SDRAM Clocks for DE-series Boards" to generate the 100MHz SDRAM clock and all seems fine. The system compile and i can program the card. My system is simple : NIOS V, JTAG_UART and SDRAM controller but when i generate bsp and try to run a test hello_world there is a problem to access memory ....
Regards
Eric
- AdzimZM_Altera
Hi Eric,
I think you should monitor the timing analysis and check for any timing violation.
If any, you should resolve that first. Can also check the clock frequency reported in the Timing report.
Regards,
Adzim
- ETang2
Hi Adzim, i will take a look to this but if somenone could share a simple project including sdram and niosV for DE10-Lite it could be helpfull ....
Regards
Eric
AvinashTh_AlteraHi Eric:
Terasic has released Nios V + SDRAM example design on DE10-LITE board. Here is path https://download.terasic.com/downloads/cd-rom/de10-lite/) Can you try this and confirm this resolves your issue. thanks
- ETang2
Hi and thanks but ths example design use nios2-gen2 which is deprecated. When i try to replace it with NiosV/m i have errors at the compilation :
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Warning (12251): DE10_LITE_Qsys.intel_niosv_m_0: Properties (associatedClock) have been set on interface reset - in composed mode these are ignoredWarning (12251): DE10_LITE_Qsys.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface instruction_manager - in composed mode these are ignoredWarning (12251): DE10_LITE_Qsys.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface data_manager - in composed mode these are ignoredWarning (12090): Entity "altera_std_synchronizer" obtained from "db/ip/de10_lite_qsys/submodules/altera_std_synchronizer.v" instead of from Quartus Prime megafunction libraryWarning (12090): Entity "altera_std_synchronizer_bundle" obtained from "db/ip/de10_lite_qsys/submodules/altera_std_synchronizer_bundle.v" instead of from Quartus Prime megafunction libraryWarning (10037): Verilog HDL or VHDL warning at de10_lite_qsys_sdram.v(318): conditional expression evaluates to a constantWarning (10037): Verilog HDL or VHDL warning at de10_lite_qsys_sdram.v(328): conditional expression evaluates to a constantWarning (10037): Verilog HDL or VHDL warning at de10_lite_qsys_sdram.v(338): conditional expression evaluates to a constantWarning (10037): Verilog HDL or VHDL warning at de10_lite_qsys_sdram.v(682): conditional expression evaluates to a constantWarning (12125): Using design file de10_lite_sdram_nios_test.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in projectInfo (12023): Found entity 1: DE10_LITE_SDRAM_Nios_TestInfo (12023): Found entity 1: DE10_LITE_SDRAM_Nios_TestWarning (10034): Output port "LEDR" at de10_lite_sdram_nios_test.v(49) has no driverWarning (10034): Output port "HEX0" at de10_lite_sdram_nios_test.v(52) has no driverWarning (10034): Output port "HEX1" at de10_lite_sdram_nios_test.v(53) has no driverWarning (10034): Output port "HEX2" at de10_lite_sdram_nios_test.v(54) has no driverWarning (10034): Output port "HEX3" at de10_lite_sdram_nios_test.v(55) has no driverWarning (10034): Output port "HEX4" at de10_lite_sdram_nios_test.v(56) has no driverWarning (10034): Output port "HEX5" at de10_lite_sdram_nios_test.v(57) has no driverWarning (10034): Output port "VGA_R" at de10_lite_sdram_nios_test.v(75) has no driverWarning (10034): Output port "VGA_G" at de10_lite_sdram_nios_test.v(76) has no driverWarning (10034): Output port "VGA_B" at de10_lite_sdram_nios_test.v(77) has no driverWarning (10034): Output port "VGA_HS" at de10_lite_sdram_nios_test.v(73) has no driverWarning (10034): Output port "VGA_VS" at de10_lite_sdram_nios_test.v(74) has no driverWarning (10034): Output port "CLK_I2C_SCL" at de10_lite_sdram_nios_test.v(80) has no driverWarning (10034): Output port "GSENSOR_SCLK" at de10_lite_sdram_nios_test.v(84) has no driverWarning (10034): Output port "GSENSOR_CS_N" at de10_lite_sdram_nios_test.v(88) has no driverError (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unionsError (10835): SystemVerilog error at riscv.pkg.sv(333): no support for unionsError (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1164): encoded value for element "MXL64" has width 32, which does not match the width of the enumeration's base type (2)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1165): encoded value for element "MXL128" has width 32, which does not match the width of the enumeration's base type (2)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1167): encoded value for element "MXL_RESERVED" has width 32, which does not match the width of the enumeration's base type (2)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1233): encoded value for element "INSTRUCTION_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1234): encoded value for element "INSTRUCTION_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1235): encoded value for element "ILLEGAL_INSTRUCTION" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1236): encoded value for element "BREAKPOINT" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1237): encoded value for element "LOAD_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1238): encoded value for element "LOAD_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1239): encoded value for element "STORE_AMO_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1240): encoded value for element "STORE_AMO_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1241): encoded value for element "USER_ECALL" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1242): encoded value for element "SUPERVISOR_ECALL" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1243): encoded value for element "MACHINE_ECALL" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1244): encoded value for element "INSTRUCTION_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5)Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1245): encoded value for element "LOAD_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5)Error (12152): Can't elaborate user hierarchy "DE10_LITE_Qsys:u0|DE10_LITE_Qsys_intel_niosv_m_0:intel_niosv_m_0|DE10_LITE_Qsys_intel_niosv_m_0_hart:hart"Error: Quartus Prime Analysis & Synthesis was unsuccessful. 20 errors, 26 warningsError: Peak virtual memory: 4778 megabytesError: Processing ended: Sat Dec 13 10:39:59 2025Error: Elapsed time: 00:01:55Error: Total CPU time (on all processors): 00:02:45Error: Peak virtual memory: 4778 megabytesError: Processing ended: Sat Dec 13 10:39:59 2025Error: Elapsed time: 00:01:55Error: Total CPU time (on all processors): 00:02:45Error (293001): Quartus Prime Full Compilation was unsuccessful. 22 errors, 26 warnings
