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ETang2's avatar
ETang2
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

DE10-Lite and sdram controller ip

Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supp...
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ETang2's avatar
ETang2
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

Hi Adzim, i will take a look to this but if somenone could share a simple project including sdram and niosV for DE10-Lite it could be helpfull ....

Regards

Eric

    • ETang2's avatar
      ETang2
      Icon for Occasional Contributor rankOccasional Contributor
      8 months ago

      Hi and thanks but ths example design use nios2-gen2 which is deprecated. When i try to replace it with NiosV/m i have errors at the compilation : 

      Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
      Warning (12251): DE10_LITE_Qsys.intel_niosv_m_0: Properties (associatedClock) have been set on interface reset - in composed mode these are ignored
      Warning (12251): DE10_LITE_Qsys.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface instruction_manager - in composed mode these are ignored
      Warning (12251): DE10_LITE_Qsys.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface data_manager - in composed mode these are ignored
      Warning (12090): Entity "altera_std_synchronizer" obtained from "db/ip/de10_lite_qsys/submodules/altera_std_synchronizer.v" instead of from Quartus Prime megafunction library
      Warning (12090): Entity "altera_std_synchronizer_bundle" obtained from "db/ip/de10_lite_qsys/submodules/altera_std_synchronizer_bundle.v" instead of from Quartus Prime megafunction library
      Warning (10037): Verilog HDL or VHDL warning at de10_lite_qsys_sdram.v(318): conditional expression evaluates to a constant
      Warning (10037): Verilog HDL or VHDL warning at de10_lite_qsys_sdram.v(328): conditional expression evaluates to a constant
      Warning (10037): Verilog HDL or VHDL warning at de10_lite_qsys_sdram.v(338): conditional expression evaluates to a constant
      Warning (10037): Verilog HDL or VHDL warning at de10_lite_qsys_sdram.v(682): conditional expression evaluates to a constant
      Warning (12125): Using design file de10_lite_sdram_nios_test.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
      Info (12023): Found entity 1: DE10_LITE_SDRAM_Nios_Test
      Info (12023): Found entity 1: DE10_LITE_SDRAM_Nios_Test
      Warning (10034): Output port "LEDR" at de10_lite_sdram_nios_test.v(49) has no driver
      Warning (10034): Output port "HEX0" at de10_lite_sdram_nios_test.v(52) has no driver
      Warning (10034): Output port "HEX1" at de10_lite_sdram_nios_test.v(53) has no driver
      Warning (10034): Output port "HEX2" at de10_lite_sdram_nios_test.v(54) has no driver
      Warning (10034): Output port "HEX3" at de10_lite_sdram_nios_test.v(55) has no driver
      Warning (10034): Output port "HEX4" at de10_lite_sdram_nios_test.v(56) has no driver
      Warning (10034): Output port "HEX5" at de10_lite_sdram_nios_test.v(57) has no driver
      Warning (10034): Output port "VGA_R" at de10_lite_sdram_nios_test.v(75) has no driver
      Warning (10034): Output port "VGA_G" at de10_lite_sdram_nios_test.v(76) has no driver
      Warning (10034): Output port "VGA_B" at de10_lite_sdram_nios_test.v(77) has no driver
      Warning (10034): Output port "VGA_HS" at de10_lite_sdram_nios_test.v(73) has no driver
      Warning (10034): Output port "VGA_VS" at de10_lite_sdram_nios_test.v(74) has no driver
      Warning (10034): Output port "CLK_I2C_SCL" at de10_lite_sdram_nios_test.v(80) has no driver
      Warning (10034): Output port "GSENSOR_SCLK" at de10_lite_sdram_nios_test.v(84) has no driver
      Warning (10034): Output port "GSENSOR_CS_N" at de10_lite_sdram_nios_test.v(88) has no driver
      Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions
      Error (10835): SystemVerilog error at riscv.pkg.sv(333): no support for unions
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1164): encoded value for element "MXL64" has width 32, which does not match the width of the enumeration's base type (2)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1165): encoded value for element "MXL128" has width 32, which does not match the width of the enumeration's base type (2)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1167): encoded value for element "MXL_RESERVED" has width 32, which does not match the width of the enumeration's base type (2)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1233): encoded value for element "INSTRUCTION_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1234): encoded value for element "INSTRUCTION_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1235): encoded value for element "ILLEGAL_INSTRUCTION" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1236): encoded value for element "BREAKPOINT" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1237): encoded value for element "LOAD_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1238): encoded value for element "LOAD_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1239): encoded value for element "STORE_AMO_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1240): encoded value for element "STORE_AMO_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1241): encoded value for element "USER_ECALL" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1242): encoded value for element "SUPERVISOR_ECALL" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1243): encoded value for element "MACHINE_ECALL" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1244): encoded value for element "INSTRUCTION_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5)
      Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1245): encoded value for element "LOAD_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5)
      Error (12152): Can't elaborate user hierarchy "DE10_LITE_Qsys:u0|DE10_LITE_Qsys_intel_niosv_m_0:intel_niosv_m_0|DE10_LITE_Qsys_intel_niosv_m_0_hart:hart"
      Error: Quartus Prime Analysis & Synthesis was unsuccessful. 20 errors, 26 warnings
      Error: Peak virtual memory: 4778 megabytes
      Error: Processing ended: Sat Dec 13 10:39:59 2025
      Error: Elapsed time: 00:01:55
      Error: Total CPU time (on all processors): 00:02:45
      Error: Peak virtual memory: 4778 megabytes
      Error: Processing ended: Sat Dec 13 10:39:59 2025
      Error: Elapsed time: 00:01:55
      Error: Total CPU time (on all processors): 00:02:45
      Error (293001): Quartus Prime Full Compilation was unsuccessful. 22 errors, 26 warnings

       

      • AvinashTh_Altera's avatar
        AvinashTh_Altera
        Icon for New Contributor rankNew Contributor
        8 months ago

        Hi Eric,

        I assume you are using 25.1 std Quartus Release and to resolve these compilation error, After you replace Nios II with Nios V/m core and generate HDL, you need to add DE10_LITE_Qsys.qip file in Quartus project files and remove .qsys file. But I see that the design implements old Avalon SDRAM controller IP and this IP is not supported in latest Quartus Standard release. And you need to use workaround mentioned earlier in this thread. thanks