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ETang2's avatar
ETang2
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1 month ago

DE10-Lite and sdram controller ip

Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supp...
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ETang2's avatar
ETang2
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

Hi AdzimZM_Altera​ and thanks for the solution that seems to work. I used "System and SDRAM Clocks for DE-series Boards" to generate the 100MHz SDRAM clock and all seems fine. The system compile and i can program the card. My system is simple : NIOS V, JTAG_UART and SDRAM controller but when i generate bsp and try to run a test hello_world there is a problem to access memory ....

Regards

Eric

SimonT's avatar
SimonT
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1 month ago

I had the same problem as well. You have to add SDC constraints.
You can take the constraints from the Eval Kit sources ./Demonstrations/SDRAM_Nios_Test/DE10_LITE_SDRAM_Nios_Test.sdc

  • ETang2's avatar
    ETang2
    Icon for Occasional Contributor rankOccasional Contributor
    1 month ago

    Thanks SimonT​ i tried this without any success.

    Eric