DE10-Lite and sdram controller ip
Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supported and I find nothing to replace it. The ddram controllers seems to be more complicated and I can’t figure out how to use their in this case. Someone coud help me ? Thanks
JTAG Chain Broken – Unable to Program Agilex 5 Modular Development Board
Hi, I recently started working with the Agilex 5 Modular Development Board, and it suddenly can no longer be programmed. The USB cable in use is known to be working. When I connect the cable, it is detected, but when I run the “Auto Detect” option in the Quartus Programmer, I receive the following message: When running the JTAG Chain Test, I see the following result: I also tried using the Configuration Debugger, but when I attempt to select the hardware cable, I encounter Error code 87: I would appreciate any help in resolving this issue, and I can provide additional details or logs if needed.
DK-DEV-AGI027RES Install Package
I'd like to download an old outdated install package. It is for DK-DEV-AGI027RES. The link was removed a while back. Can someone at Altera please find the install package for me? A .qsf file with all the pinouts (e.g. golden_top.qsf in the install package) defined would work too.
"No Video Input" message on the monitor running Display port design example for Arria 10 SX SoC
Hi, I am stuck trying to test Display Port on my Arria 10 SX SoC board. I need TX only design example. I tried to download full design example from Intel/Altera web sites, but mostly they are for older Quartus versions or for FMC daughter cards. I want to test Display Port onboard connector. My Quartus version is Quartus Pro 25.1, device - 10AS066N3F40E2SG1 Also I tried to generate design example in Platform Designer and I succeeded to receive EDID from monitor and it seems that handshake is done, but I see only "No Video Input" message on my monitor. I spend more than a week discovering the issue and I assume that PMA settings might be wrong or incorrect link rate/clock frequencies. Thanks in advance for any help!
SFP+ ref clock (program clock cleaner?)
Hi, I'm working with Arria 10 SoC dev kit and trying to use SFP+ ref clock. I don't have any information on ref clock frequency on LMK_SFPCLK(P/N) that comes from clock cleaner (U26). I need to have ref clock by like 322.265625 Mhz, so do I need to program U26 (clock cleaner)?? Where I can find the software to do so? Another question is what is the default frequency running on LMK_SFPCLK ? Thanks
LPDDR2 External Memory Controller Using Altera Cyclone V GX Dev Kit video is corrupted
Hi All, The tutorial video at: https://www.intel.com/content/www/us/en/content-details/649233/lpddr2-external-memory-controller-using-altera-cyclone-v-gx-dev-kit.html is corrupted, it will not play (only sound) and the downloaded version halts after 2min. Does anyone have or know of an uncorrupted version? Much thanks. MikeZQuestion about the schematic link for Agilex-7 F-Series Dev Kit (DK-DEV-AGF014EA)
Hello, I downloaded the schematic from this page: https://www.altera.com/products/devkit/a1jui0000049uu7mam/agilex-7-fpga-f-series-development-kit-p-tile-and-e-tile However, the schematic appears to be for a different evaluation board — it looks like a PCIe Root Complex board, not the Agilex-7 F-Series Dev Kit shown in the photo. Could you please confirm whether this is the correct schematic for the Agilex-7 F-Series Development Kit, or if the link points to the wrong file? Thank you, KashiwagiCan't find schematics, sample codes, etc. about PCI Development Board, Cyclone II Edition
The physical picture of this development board is as follows: However, I searched for a long time and only found some reference manuals, user manuals, etc. about it, but did not find the key schematics, demo programs, etc. If anyone has the factory-installed DVD disc image, could you please share it with me? Later, I downloaded a schematic from some paid forum. Although the title of the drawing was the same as that of the board, the position numbers of many components did not match. https://drive.google.com/file/d/1kWywSIMAK-OJfcWL2GlHENNIAq8T6hfI/view?usp=sharing For example, the U19 in this drawing is the Ethernet chip, but the actual device and the reference manual both say the Ethernet chip is U3. So I think this drawing is wrong. Although I found information about it in the web time machine, there is only a brief introduction and no available data for download. https://web.archive.org/web/20051226070125/http://www.altera.com/products/devkits/altera/kit-pci-2c35.html I hope some friend can help me, thank you very much
Process for RMA - Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile)
Hello there, I have an Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) (https://www.altera.com/products/devkit/a1jui0000049utomam/agilex-7-fpga-i-series-transceiver-development-kit-6x-f-tile) that has recently stopped functioning correctly. In particular, the JTAG chain does recognize the existence of the Agilex FPGA. Quartus's JTAG debugger throws an error: Error: TDI connection to the first detected device 10M16S(A|C|L) might be shorted to GND Error: The TCK and TMS connections to the device before the first detected device 10M16S(A|C|L) might have a problem Info: Detected 1 device(s) Info: Device 1: 10M16S(A|C|L) When trying different settings on the JTAG chain selection mux, it is clear that the System MAX10 is detected and functioning correctly, but the Agilex FPGA cannot be detected. We have tried to reprogram the MAX10 with the factory default image, but there has been no change. We suspect a hardware issue with the JTAG chain. At this point, the Agilex FPGA is not accesible, rendering the board unusable for our purpose. Could ALTERA please support us on this? Is it possible to start the process for an RMA? Are there any options that we can consider? We greatly appreciate your assistance in this time of need Thank you
