OneAPI for Agilex 7 I-Series Dev Kit: build-default-binaries.sh fails
Hello! I am following https://ofs.github.io/ofs-2024.2-1/hw/common/user_guides/oneapi_asp/ug_oneapi_asp/ to set up OneAPI for the Agilex 7 I-Series Development Kit (2x R-Tile, 1x F-Tile). At step 2.5.1 Compile Initialization Bitstreams the command ./build-default-binaries.sh -b ofs_iseries-dk failed with the output in the attached file. Regarding the Verilog error, I found this https://www.intel.in/content/www/in/en/programmable/quartushelp/22.1/index.htm#msgs/msgs/evrfx2_veri_opposite_direction.htm. Is there actually an error in ofs_plat_prim_burstcount1_mapping_gearbox.sv or am I doing something wrong? All tools should be the versions mentioned in the OneAPI ASP Getting Started Guide but the host OS is Ubuntu 24.04. I would appreciate some help. Thanks! Felix
receiver error for multi-simplex receivers application (transceiver arria 10)
Hi all, FPGA : 10AX115N2F45E1SG simplex rx count : 16 pin assignment : four channel from 4c, four channel from 4d, four channel from 4e,four channel from 4f. ref clock : single 62.5Mhz from 4e bank power of transceiver : 1.03V (1_0V in IP, short reach). connection : chip 2 chip (two 10ax115N2F45E1SG fpga board, one is TX, one is RX) link loss < 10DB Speed : 1Gbps/2Gbps/5Gbps. issue : for some boards, it could receive pattern correctly (1/2/5Gbps); some board, there's error for some lane(1/2/5Gbps) when we run prbs18 test. For the board with error, we run the loopback test, there' no error. analysis: We check the eye diagram after ac-couple about the error lane, it's eye height and eye width is okay; and they all can pass loopback test. So I think there's problem at RX analog frontend, and we check the refclk and power supply, it's okay. I do not know which factor will I need to consider except that. Could someone help me? BRs, LambertCyclone 5 first boot linux crashes, howto debug?
Hello, We have a design with a Cyclone V FPGA. Some boards only boot after a reset following power-on. Problem: The Debian Linux with U-Boot boots from the SD card, but after approximately 10 seconds, the system crashes and becomes unresponsive. The login prompt appears (on UART debug), but I cannot enter anything, and the network interface does not work. How should I start troubleshooting? There is a JTAG on the board, but I have never used it until now. Any hints or links would be greatly appreciated. Sorry, but I have no idea how to resolve this, or where to start with the troubleshooting.
Intel® FPGA Technical Training for every public users
Dear all, Altera FPGA technical training offers many ways to learn. Sharpen your FPGA design skills today! All public training is free to attend. Training includes: Instructor-led Classes On-Demand eLearning Webinars and Workshops Quick Videos and many more Certified Intel FPGA Training Partners are available to teach in the following regions of the world: Africa, Asia, Australia and New Zealand, Europe, India, Israel, and South America. Click here Altera® FPGA Technical Training for more details. Kind regards, Altera Support Team
FPGA to HPS bridge on Agilex 7
Hello I'm trying to read and write from and to HPS SDRAM on Agilex 7 board I have this configuration of fpga2hps interface: On the other side I have two msgdma ip cores for MM to Stream and Stream to MM transfers. But MM to Stream DMA doesnt work as its busy bit is permanently set to 1. As I understood from reading the forum it can be related to fpga2sdram bridge which is not initialized right. So my question is: 1) how to make sure my fpga2sdram bridge is in the right condition 2) what can be wrong with the MM to Stream DMA? DMA settings: FPGA to HPS AXI bus state:
KITRON_29_LIFECYCLE STATUS_ROHS_REACH_
Hello, I am Donald from TechAdvance Solutions. We are contracted by KITRON, to assist them in obtaining the subject data for the parts supplied by you. Please find the attached LOA from your Customer authorizing the same. The attached spreadsheet lists the parts supplied by you, for which the Customer is seeking the subject information. The cells which are blank are the ones which we are unable to get the information from your website. Kindly provide the below for the attached part list : Lifecycle Status : (Active/Obsolete/EOL/NRND) Last Time Buy (LTB) date ( If the input part is EOL ) RoHS 3 (2015/863/EU) Certificate of Compliance (URL/File Name) Alternate RoHS Compliant part if the input part is Obsolete/EOL/NRND/Non-RoHS REACH 235 SVHC certificate of Compliance (URL/File Name) SCIP reference number for SVHC present parts I would appreciate if you could provide us the information and send to us in Two Business Days . Just in case you are not able to comply to this request, please let us know by what date you will be able to. Feel free to contact me for any clarifications/ information. Thank you in advance. Regards, Donald Sourcing Engineer TechAdvance SolutionsStratix 10 MCDMA host: Queue reset failed
Hello, I have been trying to get an MCDMA example design working on a Stratix 10 MX device (1SM21BEU2F55E2VG). You can consider me a beginner with the Intel FPGAs. The project details are as follows. Device side ----------------- Project: Platform designer project with H-tile PCIe MCDMA with AVMM interface. PCIe configuration - Gen3x16 512-bit interface, 250 MHz No of PFs - 1 Everything else is set to default, as this is a slightly modified version of the basic example design generated by Quartus. refclk - connected to differential PCIe clock PCIE_REFCLK_P and PCIE_REFCLK_N pin_perst - connected to PCIe PERST# npor - tied to 1 in the top level wrapper Verilog module xcvr - PCIe interface The top-level wrapper only instantiates this, sets npor to 1, and passes every other signals. The hip_ctrl and hip_pipe are left unconnected in the wrapper. The design compiles properly, and the sof file can be programmed without error. ----------------------- Host side ----------------------- On the host side, I followed the steps mentioned in the MCDMA example user guide. https://www.intel.com/content/www/us/en/docs/programmable/683517/23-4/introduction.html The device is listed the lspci output and shows up the BAR regions. However, when I try to run any of the test programs in the software/user/cli, nothing runs successfully (this driver and user utilities/examples are also generated as part of the example MCDMA project). Most of the time the error is "Queue reset failed" or the programs hang without any output. Reading device memory via the supplied devmem utility always returns 0xFFFFFFFF. My guess is something wrong with the reset logic/process, however I am unable to fix it so far and it feels like I am missing something obvious. Any lead in this regard would be helpful. Let me know if you need more information in this context. Thanks and regards, ArnabAltera USB Blaster (usb-0)
Hi all, i have a device which used fpga cyclone v 5CEBA4U15C7, iam using quartus prime lite 19.1, my goal is to access this fpga device through a jtag connection (connections are done) and flash sof files and view how the fpga works, The altera usb blaster iam having is altera usb blaster (not usb blaster ii, in programmer the hardware will show this device as USB-0). This usb blaster is not recognizing my fpga, instead, it is showing 5ceba4, the exact part number is not showing, and iam not able to flash my sof files, even if i selec 5ceba4 and flash via jtag, programmer will show that it's failed, should i get a usb blaster ii ? in the data sheet of usb blaster (USB-0) it is shown that it supports cyclone V EPCQ-L devices, in the data sheet of usb- blaster (USB-II) it is shown that it supports Cyclone v FPga devices, i just wanted to confirm whether this is due to usb-0 not supporting my exact fpga board, or should i get usb-ii for accessing my exact fpga device. Thanks in advance, mahesh. this is how usb blaster is shown in device manager.
