FPGA to HPS bridge on Agilex 7

Hi,

For the mSGDMA IP core, you can refer to the Embedded Peripherals IP UG:

https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/modular-scatter-gather-dma-core.html

For the bridge setup, please refer here for the full documentation on what you can do:

https://www.rocketboards.org/foswiki/Projects/SettingUpAndUsingBridgesOnAgilex

If you have further questions on the setup, let me know.

Hi,

Do you have any further questions?

Hello!

Thank you for your answer.

I've been able to run my fpga design, and it seems there was something wrong with u-boot.

The problem now is that when I run my board with Linux booted from SD card fpga design doesn't work and the system hangs when I try to read or write to FPGA memory space. But somehow when I make U-boot not able to read FPGA bitstream from the SD card and do reboot everything works completely fine. I use HPS boot first config, so my bitstream is located on SD card. To summarize the process:

1. Boot system as usual, FPGA will be programmed.

2. go to /run/media/mmcblk0p1/ directory where FPGA bitstream is located

3. rename fpga bitstream to any name, just to make sure u-boot won't find it

4. reboot system and you will see that U-Boot wasn't able to program FPGA

Failed to load 'fpga_bitstream.rbf'
FPGA not ready. Bridge reset aborted!

5. wait until system boot is over, login

Now after these steps I can use FPGA.

For building SD card image I've used this link
https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderAgilex7?erpm_id=12888127_ts1687163227736

It seems something is wrong after FPGA programming and it can be fixed by something U-Boot does before programming FPGA. I've tried to add more

bridge enable

or

bridge disable

commands to CONFIG_BOOTCOMMAND but that didn't help.

I use the latest commit of socfpga_v2022.10 branch in u-boot-socfpga repository.

Hi,

Thanks for the info, I may need some time to digest it and I will get back to you.

Just to be sure again, you can do read/write to FPGA in Linux environment, if you do not configure the FPGA in U-boot in prior boot stage?

One more question has just recently arised.

When I try to read from HPS SDRAM I get RRESP == 3. The address I use for read operation is provided by Linux driver (physical address like 0x2A377D802) and it is supposed to point to SDRAM region.

So my question is: do I need to somehow change read/write address before read or write through fpga2sdram bridge?

Hi,

On the new questions, do you have a screenshot for that? I would like to take a look.

Hello

Unfortunately no, but it is a typical read transaction with RRESP == 3 and RDATA is set to all zeros.

I've set "Interface destination" option to CCU and got everything work alright with addresses Linux gives me. But for the final design I don't need my SDRAM access transactions to go through CCU. So it is ok as a temporary workaround but I still need to be able to access SDRAM directly.

Hi,

Just checking again, if you do normal boot without interruption to Linux, it will boot just fine?

My guess would be the bridge must be disable again in Uboot before loading the Kernel and Linux.

Hi,

Meaning to say, you would just let it boot upon power cycle and do not do anything in Uboot environment etc.

Also, want to check are you using the ATF? Arm Trusted Firmware.