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Contributorreceiver error for multi-simplex receivers application (transceiver arria 10)
Hi all,
FPGA : 10AX115N2F45E1SG
simplex rx count : 16
pin assignment : four channel from 4c, four channel from 4d, four channel from 4e,four channel from 4f.
ref clock : single 62.5Mhz from 4e bank
power of transceiver : 1.03V (1_0V in IP, short reach).
connection : chip 2 chip (two 10ax115N2F45E1SG fpga board, one is TX, one is RX)
link loss < 10DB
Speed : 1Gbps/2Gbps/5Gbps.
issue : for some boards, it could receive pattern correctly (1/2/5Gbps); some board, there's error for some lane(1/2/5Gbps) when we run prbs18 test. For the board with error, we run the loopback test, there' no error.
analysis: We check the eye diagram after ac-couple about the error lane, it's eye height and eye width is okay; and they all can pass loopback test. So I think there's problem at RX analog frontend, and we check the refclk and power supply, it's okay. I do not know which factor will I need to consider except that.
Could someone help me?
BRs,
Lambert
18 Replies
ZiYing_IntelFrequent Contributor
Hi lambert,
Thanks for submitting the issue. Allow me have some time to look into the issue and I will get back to you with findings.
Best regards,
zying
- ZiYing_Intel
Hi lambert,
Thanks for submitting the issue. Allow me have some time to look into the issue and I will get back to you with findings.
Best regards,
zying
- ZiYing_Intel
Hi lambert,
cand you share the .qar file? So that I can try debug the issue from my side.
Best regards,
zying
lambert_yuHi ZiYing,
From our current debug, we found that keep all design as before, and decrease the VOD of TX (1000mv -> 600mv (other value, we have not try), 1.0Gbps/2.0Gbps, other we do not try), there's good performance for the receiver. But on the view of our hardware designer, they think at 1.0Gbps, tx should not lead to so large effect on the receiver when Vod at 1000mv. They think from the eye diagram after ac-coupling capacitance, it's sufficient for RX to receives data correctly.
I could not provide related design for you, but I will provide related parameter and application framework next.
BRs,
Lambert
- lambert_yu
Hi ZiYing,
The attached is the related configuration pictures and connection framwork. Please check, thanks.
BRs,
Lambert
- ZiYing_Intel
HI lambert,
Could you try to do the reverse loopback?
Best regards,
zying
- lambert_yu
Hi Zying,
I am sorry that we could not do the reverse loopback test because that we do not have theis daugther baord to do this thing currently.
For the previous configuration of IP, do you think there's any problem which I should note? (Now we only require our boards to support up to 5Gbps).
For simplex RX, we use manual mode to do lock-to-ref and lock-to-data.
cal_busy _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ //_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ana reset ------------------------------------------------------|_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ //
locktoref ----------------------------------------------------------------------------------------------//--------|_ _ _ _ _ _ _ _ _ _ _ _ _
|<----------- long time ------------------------>|
tx_data_output _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ //--------------
locktodata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _|-------------------------
dig reset -----------------------------------------------------------------------------------------------------------------------|_ _ _ _ _ _ _
For this reset solution, is there any issue?
And, about the board design for the voltage of VCCTR_GXB/VCCH_GXB/VCCPLL_GXB as the attached, do you think this is okay for so many channels work at the same time? (VCCTR_GXB decoupling to 2.6A, now work current is 2.5A, is there problem?)
BRs,
Lambert
- ZiYing_Intel
Hi lambert_yu,
I think maybe you need concern about the voltage that you use. It has the minimum and maximum voltage requirement for different usage. For further information, you may refer link below https://www.intel.com/content/www/us/en/docs/programmable/683771/current/transceiver-performance-for-gx-sx-devices.html
Best regards,
zying
- lambert_yu
Hi Zying,
Now we use chip-to-chip design, and our fpga is 10ax115n2f45e1sg, so I think it's okay for VCCTR_GXB = 1.03v (in the below attached picture), do you think so?
In the previous picture, we mark VCCTR_GXB as 1V, now we had changed it to 1.03v on board now.
BRs,
Lambert
- ZiYing_Intel
Hi Lambert_yu,
Can you share me your simulation result? So I can see the things from the signal
Best regards,
zying
- lambert_yu
Hi zying,
Which signals will you expect me to provide? The interface signal of transceiver or anyother? Firstly, I will provide 3 transceiver interface signal, please check. If you need more detail, please tell me and I will capture them and provide to you.
Brs,
Lambert
- ZiYing_Intel
Hi lambert,
I would suggest you can try to reduce the BER by increasing the amplitude or the main tap. If the suggestion still not working for you, you may refer to link below https://www.rocketboards.org/foswiki/Main/WebHome that got a lot of project that you can refer to.
Best regards,
zying
- lambert_yu
Hi zying,
Sorry, I could not understand these method? increase amplitude ? TX vod? But from previous message, I mentioned that link is okay when I decrease Vod; What's main tap? DFE or other?
BRs,
Lambert
- ZiYing_Intel
Hi lambert,
Is there any update from you?
Best regards,
zying
- ZiYing_Intel
Hi Lambert,
Can you share your .qar file? So that i can try debug the issue from my side.
Best regards,
zying
- ZiYing_Intel
Hi Lambert,
Is there any update from your side?
Best regards,
zying
- lambert_yu
Hi Zying,
From the test result, I think there's issue at our link, and after I modified the EQ value of RX, now cases passed.
BRs,
Lambert
