receiver error for multi-simplex receivers application (transceiver arria 10)

Hi ZiYing,

From our current debug, we found that keep all design as before, and decrease the VOD of TX (1000mv -> 600mv (other value, we have not try), 1.0Gbps/2.0Gbps, other we do not try), there's good performance for the receiver. But on the view of our hardware designer, they think at 1.0Gbps, tx should not lead to so large effect on the receiver when Vod at 1000mv. They think from the eye diagram after ac-coupling capacitance, it's sufficient for RX to receives data correctly.

I could not provide related design for you, but I will provide related parameter and application framework next.

BRs,

Lambert

Hi ZiYing,

The attached is the related configuration pictures and connection framwork. Please check, thanks.

BRs,

Lambert

Hi Zying,

I am sorry that we could not do the reverse loopback test because that we do not have theis daugther baord to do this thing currently.

For the previous configuration of IP, do you think there's any problem which I should note? (Now we only require our boards to support up to 5Gbps).

For simplex RX, we use manual mode to do lock-to-ref and lock-to-data.

cal_busy _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ //_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

ana reset ------------------------------------------------------|_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ //

locktoref ----------------------------------------------------------------------------------------------//--------|_ _ _ _ _ _ _ _ _ _ _ _ _

|<----------- long time ------------------------>|

tx_data_output _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ //--------------

locktodata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _|-------------------------

dig reset -----------------------------------------------------------------------------------------------------------------------|_ _ _ _ _ _ _

For this reset solution, is there any issue?

And, about the board design for the voltage of VCCTR_GXB/VCCH_GXB/VCCPLL_GXB as the attached, do you think this is okay for so many channels work at the same time? (VCCTR_GXB decoupling to 2.6A, now work current is 2.5A, is there problem?)

BRs,

Lambert

Hi Zying,

Now we use chip-to-chip design, and our fpga is 10ax115n2f45e1sg, so I think it's okay for VCCTR_GXB = 1.03v (in the below attached picture), do you think so?

In the previous picture, we mark VCCTR_GXB as 1V, now we had changed it to 1.03v on board now.

BRs,

Lambert

Hi zying,

Which signals will you expect me to provide? The interface signal of transceiver or anyother? Firstly, I will provide 3 transceiver interface signal, please check. If you need more detail, please tell me and I will capture them and provide to you.

Brs,

Lambert

Hi zying,

Sorry, I could not understand these method? increase amplitude ? TX vod? But from previous message, I mentioned that link is okay when I decrease Vod; What's main tap? DFE or other?

BRs,

Lambert

Hi Zying,

From the test result, I think there's issue at our link, and after I modified the EQ value of RX, now cases passed.

BRs,

Lambert