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lambert_yu's avatar
lambert_yu
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3 years ago

receiver error for multi-simplex receivers application (transceiver arria 10)

Hi all, FPGA : 10AX115N2F45E1SG simplex rx count : 16 pin assignment : four channel from 4c, four channel from 4d, four channel from 4e,four channel from 4f. ref clock : single 62.5Mhz f...
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ZiYing_Intel's avatar
ZiYing_Intel
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3 years ago

Hi lambert,


cand you share the .qar file? So that I can try debug the issue from my side.


Best regards,

zying


  • lambert_yu's avatar
    lambert_yu
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    3 years ago

    Hi ZiYing,

    From our current debug, we found that keep all design as before, and decrease the VOD of TX (1000mv -> 600mv (other value, we have not try), 1.0Gbps/2.0Gbps, other we do not try), there's good performance for the receiver. But on the view of our hardware designer, they think at 1.0Gbps, tx should not lead to so large effect on the receiver when Vod at 1000mv. They think from the eye diagram after ac-coupling capacitance, it's sufficient for RX to receives data correctly.

    I could not provide related design for you, but I will provide related parameter and application framework next.

    BRs,

    Lambert

  • lambert_yu's avatar
    lambert_yu
    Icon for Contributor rankContributor
    3 years ago

    Hi ZiYing,

    The attached is the related configuration pictures and connection framwork. Please check, thanks.

    BRs,

    Lambert