Workaround for TCK frq. limitations on USB-Blaster I/II/III & Clones (fixing "JTAG chain broken")

Workaround for TCK frequency limitations on USB-Blaster I/II/III and clones (fixing "JTAG chain broken")

Hi everyone,

I'd like to share a practical workaround for a problem many of us run into when programming Altera FPGAs through test fixtures, level shifters or long ribbon cables.

**The problem**

In these setups, "JTAG chain broken" or "Unable to scan device chain" errors are common. They are usually caused by signal reflections and poor termination on custom boards and long extensions. Lowering the TCK frequency is the standard remedy, but the options are limited:

- USB-Blaster I (and most low-cost clones) runs at a fixed TCK of about 6 MHz. Quartus offers no way to change it.

- USB-Blaster II can be set to 6/16/24 MHz via `jtagconfig --setparam <cable> JtagClock <freq>`, but nothing below 6 MHz. In practice this setting is also unreliable: it is not persistent and can fall back to the 24 MHz default (see Altera KB: "Why does the TCK frequency setting of the USB-Blaster II download cable revert to the default value of 24 MHz after being changed?"). In our experience it is a constant source of trouble, especially in production where it has to be set again and again.

For really marginal lines, 6 MHz is often still too fast.

**The workaround**

Disclosure: I'm the developer of the tool described below, so please take this as information from the vendor.

Quintus Programmer (by Dution) drives the JTAG lines of the USB-Blaster in bit-bang mode instead of using the adapter's fixed shift clock. This lets you choose the TCK frequency freely, e.g. down to 100 kHz, with the same USB-Blaster I/II/III or clones you already have.

With a lower TCK, programming and verification become stable again on long or poorly terminated lines without any hardware changes. The standard USB-Blaster driver stays in place, and Quintus only replaces the programming step.

**Before reaching for software, check the hardware basics**

The recommendations from the Altera Knowledge Base still apply and often fix the problem on their own:

- TCK pull-down 1 kΩ to GND, TMS/TDI pull-up 10 kΩ to VCCIO

- a small capacitor (10–22 pF) at TCK near the FPGA against ringing edges

- a TCK buffer on long or noisy lines

If the layout can't be changed, a lower TCK is a practical way out. More info: search for "Quintus Programmer Dution".

Happy to answer technical questions here.