DK-DEV-AGI027RBES missing device selection
Hi, Saw similar issues on slightly different part numbers. I have the following ES2 development board: DK-DEV-AGI027RBES which has the AGIB027R29A1E2VR3 device part number. I couldn't find this part number in Quartus Pro 26.1 nor older versions like Quartus Pro 23.3 Furthermore, when running JTAG scan in 23.3 it seems like IDCODE is shared across multiple devices where neither of them is the part I have: Quartus 23.3 device selection does show the part I have: I prefer working with 26.1 and receiving a patch to support this part number if possible, if not please guide which Quartus version is best to use in my case. Thanks!
in MAX 10 Dev kit
Hi Altera Community, I am encountering a JTAG Server Error Code 35 when attempting to program my MAX 10 Development Kit using the USB-Blaster. Below are the details of my setup and the issue: Board: MAX 10 Development Kit Programmer Cable: USB-Blaster Problem Description: When opening the Quartus Programmer and clicking Start (or running Auto Detect), the process fails with the following log: Error (209053): Unexpected error in JTAG server -- error code 35 Error (209040): Can't access JTAG chain
Cyclone® 10 GX FPGA Development Kit (Version B) DK-DEV-10CX220-B Installer Package (v22.4 or higher)
Good morning, I'm trying to donwload the Installer package for DK-DEV-10CX220-A and or B from altera website, but i'm getting always error 502. https://docs.altera.com/v/u/resources/649830/cyclone-10-gx-fpga-development-kit-version-a-dk-dev-10cx220-installer-package-v22.4-or-higher https://docs.altera.com/v/u/resources/838158/cyclone-10-gx-fpga-development-kit-version-b-dk-dev-10cx220-b-installer-package-v22.4-or-higher I tried from Windows, linux and with different PCs but is always the same, so assume the Server is down or the installation file has been remove. Can someone please reuplaod it for me? Thanks Xavier Ruiz
SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design
Hi, In Agilex 7 M-Series Evaluation Kit clock tree, the 390.625 MHz SyncE (Synchronous Ethernet) recovered/reference clock is distributed through the Si5395/Si5391 clock generators and is used to generate clocks for the DDR5, HBM, and FPGA control/SDM interfaces. My understanding is that a recovered SyncE clock is primarily intended for Ethernet frequency synchronization. Therefore, I am trying to understand the design rationale behind using it as the master reference for non-Ethernet interfaces on the board. Could someone please clarify: Why is the SyncE clock chosen as the primary reference for generating DDR5, HBM, and FPGA control interface clocks? What are the advantages of using the SyncE reference instead of a dedicated crystal oscillator or another fixed-frequency reference? Is this done to maintain frequency synchronization across the entire system, or are there other design considerations such as clock quality, jitter performance, or timing alignment? Is this approach recommended only for the evaluation board, or is it also the recommended clocking architecture for custom Agilex M-Series designs? Any explanation or reference to the relevant Intel documentation would be greatly appreciated. Thank you.Why 390.625MHz clock to F-Tile Reference fequency
Hi, This question is regarding the Agilex 7 M-Series FPGA Development Kit. In the evaluation board schematics, the Si5518 provides a 390.625 MHz clock that is connected to two F-Tile reference clock inputs. From the F-Tile Ethernet Hard IP User Guide, I understand that standard Ethernet designs typically use 156.25 MHz as the PMA reference clock, while the 390.625 MHz clock appears internally as the clk_txmac/clk_rxmac clock. My questions are: 1. Which F-Tile configuration or interface is intended to use the external 390.625 MHz reference clock on the development board? 2. Is this reference intended for the Ethernet Hard IP, PMA Direct mode, SyncE, or some other transceiver application? 3. Are there any official reference designs that use this 390.625 MHz reference clock? I would appreciate it if you could clarify the intended use of this clock on the Agilex M Development Kit. Regards,Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs
Hello, I am developing a custom PCIe endpoint using the Agilex 7 R-Tile PIPE Direct interface. The PHY is provided by the R-Tile IP, while the LTSSM, Data Link Layer, and TLP/DLLP handling are implemented in soft RTL. Environment FPGA: Agilex 7 AGIB027R29A Quartus Prime Pro 24.3.0 Build 212 R-Tile PIPE Direct mode PCIe Gen3 x8 Custom soft LTSSM and Data Link Layer Linux host with a commercial PC/root complex The FPGA is configured before a host cold boot The endpoint is not currently visible in lspci In a successful Signal Tap capture: The LTSSM reaches Gen3 L0. The Data Link Layer reaches DL_ACTIVE. InitFC1 and InitFC2 for Posted, Non-Posted, and Completion traffic are exchanged. We observe valid incoming TLP traffic with a correct LCRC. The host sends a Message TLP that appears to decode as Set_Slot_Power_Limit. No subsequent Configuration Type 0 Read TLP or other expected enumeration TLP is observed. The link later returns from L0 to Recovery.RcvrLock. Our understanding is that Set_Slot_Power_Limit is a posted Message TLP and should not require a Completion TLP from the endpoint. The endpoint should only acknowledge successful reception at the Data Link Layer. Please correct us if this interpretation is wrong. Questions Is receiving Set_Slot_Power_Limit before the first Configuration Read a normal root-port enumeration sequence? Does the endpoint need to respond to this Message TLP in any way other than sending a Data Link Layer ACK? If the ACK DLLP has an incorrect sequence number, CRC, or timing, could the root port stop sending further TLPs and eventually force the link into Recovery? Are there any R-Tile PIPE Direct-specific status or control signals that must be handled before the host starts Configuration transactions? Are there recommended R-Tile debug signals for determining why the root port stops after this message? Could an incorrect Flow Control advertisement—especially Completion Header/Data credits—cause this behavior even if InitFC2 completes? Are there known PERST#, cold-boot, or FPGA-configuration timing requirements for enumeration when using PIPE Direct mode? We are currently capturing the following signals: LTSSM state Data Link Layer state InitFC1/InitFC2 and UpdateFC status Received TLP Fmt/Type and complete header Received TLP sequence number LCRC result ACK/NAK request and transmitted ACK/NAK sequence number Replay timer/replay status RX block lock, CDR lock, and lane numbers Raw 1024-bit PIPE RX block data Any guidance on the expected transaction sequence after Set_Slot_Power_Limit, or additional signals that should be captured, would be greatly appreciated. Thank you.
R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work
We recently generated an R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK DEV AGM039EA) with both Quartus Prime Pro 25.3.1 and 26.1. However, the CXL link is always down and stuck at Gen1 2.5Gbps. Do you have any suggestions, or is there a working CXL design example for this kit? We verified that the link functions perfectly with a PCIe Gen5/Gen4 example.We recently generated an R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK DEV AGM039EA) with both Quartus Prime Pro 25.3.1 and 26.1. However, the CXL link is always down and stuck at Gen1 2.5Gbps. Do you have any suggestions, or is there a working CXL design example for this kit? We verified that the link functions perfectly with a PCIe Gen5/Gen4 example.
DE10-Lite and sdram controller ip
Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supported and I find nothing to replace it. The ddram controllers seems to be more complicated and I can’t figure out how to use their in this case. Someone coud help me ? Thanks
