Stratix 10 GX SI Board - issue with the Board Test System (BTS)
We recently purchased several Stratix 10 GX Signal Integrity development boards and would appreciate your advice regarding an issue with the Board Test System (BTS). When attempting to program the FPGA using the .sof files available under the Configure tab in BTS, none of the designs can be successfully programmed. The system consistently reports: “Detected bts_config.sof on FPGA.” It appears that the FPGA remains running the default bts_config.sof, and the selected configurations do not load as expected. This happens when the Quartus version in the QUARTUS_ROOTDIR is the Quartus standard. If I change it to Quartus Pro version ( I tried 22.1 24.1 and 25.1), the BTS will not be open, and it gets stuck at "Setup connection to System Console server". Could you please let us know whether this is a known issue and advise on how to resolve it? I think it might be related to the version of Quartus we use. If so, please can you suggest which latest version we should use for the BTS? Thank you very much for your assistance. Best regards, Toni771
Available replacement for the discontinued P/N: MK-A5E065BB32AES1 ?
Hello, PDN: https://www.mouser.com/PCN/Intel_Corporation_PDN2513.pdf?srsltid=AfmBOoqEg4CcKdQVpDMH8g2nQDlihxYoQoJwu3Bcg91PBuKx__G1W-Mf is suggesting P/N: MK-A5E065BB32AEA (Future) as replacement for the already discontinued P/N: MK-A5E065BB32AES1 A customer is desperately searching for this old or the new board, or an alternative that would be immediately available for an important project. His previous order was not considered any more, unfortunately. Can you possibly help to get hold of one of these boards, or would you know a reseller who might still have stock? Thank you very much Best regards Adnan (ref: Q1CDFE8)
Differential Signal Transmitter on Agilex 5 FPGA Modular Dev Kit
We will use the SOM Module of the Agilex 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1) for a new project with our own designed carrier board. For this design we need multiple differential transmit and receive signals from I/O Bank 2A_B and 2A_T (→ 1.2V bank supply). We started with a basic design to evaluate usable I/O Standards. We have seen that we can use differential receiver with the 1.2V bank supply but it is not possible to use "True Differential Signaling" on transmit pins with 1.2V bank supply. For our purpose it is necessary to generate differential transmit signals correctly working with LVDS inputs on the receiver site. Is there an alternative differential signal output generating a correct LVDS signal for a LVDS receiver working with the 1.2V bank supply (e.g. POD12 with special termination)? What happens when setting differential transmit and receive pins to "1.3V True Differential Signaling" to get Quartus running without an error but physically using only 1.2V bank supply? Will this only decrease signal swing on transmit pins or is this not working? Or could this damage the FPGA transmit and receive pins of the FPGA? The SOM schematic does not show any possibility to disconnect the I/O Banks 2A_B and 2A_T from onboard 1.2V supply to use an alternative external 1.3V supply. Is there the a possibility to supply these banks externally by 1.3V? Which other alternatives do we have to get differential signaling output working?DK-SI-AGI040FES KIT: Agilex™ 7 F-Series and I-Series ES Device Errata
Hello ! Please help us to get this errata document. We got Agilex-7 I-Series Kit ES1 6xF-Tile (DK-SI-AGI040FES) with AGIC040R39A2E2VR0 device and need errata document for ES1 device to departure from kit package sample designs with clear understanding ES1 device limitation while building own designs for the device in the kit. All applications through Intel access gets all time denials without any explanations, links and even FAE contact information. Wasted $15K on this kit and cannot get any support, terrible experience with Intel. This ES errata document is mentioned in Agilex™ 7 F-Series and I-Series Known Issue List. https://docs.altera.com/r/docs/683584/current/agilextm-7-f-series-and-i-series-known-issue-list/about-this-document Here is screenshot Its also still available in old I-series datasheets that are hosted on Mouser and Digikey: https://www.mouser.com/pdfDocs/ug-agilex-i-fpga-devl-kit-683288-6772523.pdf Here is screen shot: This is link to get datasheet but I cannot get permission to it: https://cdrdv2.intel.com/v1/dl/getContent/612877?explicitVersion=true !!! AND PLEASE DO NOT DELETE MY QUESTIONS !!!! Best regards, SamDK-SI-AGI040FES KIT: Agilex™ 7 F-Series and I-Series ES Device Errata
We got Agilex-7 I-Series Kit ES1 6xF-Tile (DK-SI-AGI040FES) with AGIC040R39A2E2VR0 device and need errata document for ES1 device to departure from kit package sample designs with clear understanding ES1 device limitation while building own designs for the device in the kit. All applications through Intel access gets all time denials without any explanations, links and even FAE contact information. Wasted $15K on this kit and cannot get any support, terrible experience with Intel. This ES errata document is mentioned in Agilex™ 7 F-Series and I-Series Known Issue List.DK-SI-AGI040FES KIT: Agilex™ 7 F-Series and I-Series ES Device Errata
We got Agilex-7 I-Series Kit ES1 6xF-Tile (DK-SI-AGI040FES) with AGIC040R39A2E2VR0 device and need errata document for ES1 device to departure from kit package sample designs with clear understanding ES1 device limitation while building own designs for the device in the kit. All applications through Intel access gets all time denials without any explanations, links and even FAE contact information. Wasted $15K on this kit and cannot get any support, terrible experience with Intel. This ES errata document is mentioned in Agilex™ 7 F-Series and I-Series Known Issue List.The old NIOS development kit, Stratix edition: factory demo image.
I have some of the boards, but one of them isn't able to run the demo code, there are no blinking LEDs. Moreover, the factory demo images of both NIOSII EDS 5.1 and 7.0 didn't work, that's funny. After reading back flash from one of the boards, the backup factory demo image worked as expected. But one other board is still not able to run code, stay in an ambiguous state (CPU reset state?), factory safe LED lights. Are there some things to check by the factory demo image? Why does it hold on running the factory demo code? SDRAM failure? The user bitstream (no NIOS II) is OK to run from the flash.
MAX10 10M50 Development KIT Triple Speed Ethernet problem
Greetings to all of the ALTERA Experts, I have been trying to get a Gigabit Ethernet interface working on an ALTERA MAX10 10M50-C Development kit and keep hitting a bit of a brick wall when tying to communicate with the MARVEL ALASKA 88E1111 PHY. It does not appear to respond correctly when i try to read for example the PHY ID register (address x02) which should respond with the value 0x041 but instead sends back 0x7fff. I am using a System Verilog HDL approach to both instantiate the ALTERA Triple speed IP core in MAC only mode, with 2K word FIFOs, and full duplex 10/100/1000. The IP is set to work in Gigabit mode. When i connect the board to a windows 10 PC using an Ethernet cable i can see the Yellow LED lit up on the Dev KITS PHY connector and when i test the connection on the windows 10 PC it says it is up and connected. But when i try to send any Ethernet packets (i am using IPV4 + UDP as packet payload) nothing gets through to the PC. I have verified this as well using WIRESHARK which shows me no ethernet frames are coming in from the MAX10 Dev kits end. I have set the Triple speed Ethernet IP cores mac0/mac1 register to this random value: 48'h321C23174ACB I think this is OK and what the Triple Speed Ethernet User Guide says. Please correct me if my thinking is wrong though ? Questions: a) Does any body know of any errata / bugs with this Development KIT OR with the MARVELL PHY ? b) Can anybody point me to a Git Hub which has a known working example using this ALTERA Dev Kit along with this MARVELL PHY ? This can use either a HDL approach (like i am trying to use here) or a NIOSV softcore processor approach. c) The MAX10 Dev Kit has 2 Ethernet PHYS. A and B. I think that the MAX10 10M50-C Dev Kit sets its A MARVELL PHY Address to 0x0 and its B side MARVELL PHY Address to 0x1 BUT its not easy i found to figure out the PHY addresses. If somebody can please show me how to properly derive the PHY ADDRESSES for both the MARVELL 88E1111 devices for PHY A (ETHERNET A) and PHY B (ETHERNET B) on the MAX10 10M50-C Dev Kit Board Schematic) i will be very grateful ! Thanks for any help, Dr Barry H
