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New ContributorCold Temperature Issue
New ContributorHi,
just a short question (do not want to deter this thread): how did you detect it is not out of POR?
(maybe relevant maybe not) On 2 out of 50 Agilex3 devices we have met with similar issue and resulted that over JTAG idcode was read as F36FF0DD instead of 4365B0DD. Is it equivalent to this same issue that SDM ROM code is not coming out of POR? do you observe similar behavior?
How does your power topology looks like?
We have 1.8V and 3.3V HVIO and if 3.3V HVIO's VCCIO do not get some minor accidental backfeed which raises it to 0.6V then FPGA stays in POR.
Voltage rail sequence is 0.75V -> 1.8V -> 1.2V -> 3.3V.
Is it ok to bring up 1.8V SDM and 1.8V VCCIO at the same time or should we bring up the 1.8V+3.3V VCCIO after 1.2V?
Thanks,
Peter
Asaf_BlochHi dpcsu,
Thanks for your reply
Our voltage rail sequence is VID, 08V -> 1.8V -> 1.2V, 3.3 VCCIO
We detect the POR issue because we don't see any signal transitions after power up (nStatus, PMBus), JTAG detect the device.
How did you read the SDM ROM?
Any way we repeat the test with other PCB and it pass successfully, so we examine if it specific PCB issue.
regards
Asaf
- dpcsu_e
Hi Asaf,
thanks!
I did not read ROM code out, it is assumed that SDM ROM code did not startup properly since the JTAG IDCODE is not fully populated.
My assumption that it is (like in many hardware platforms, not just at altera) reading out some fuses to see what FPGA the ROM code sits and populating the IDCODE accordingly (that's where I could see F's instead of the real digits when boot is not correct, you can also check if you end up similarly (it is much easier to detect than reading i2c bus traffic)). If SDM ROM code starts up properly then those digits are populated and the rest is probably coming from hardwired JTAG logic (that's the only reasonable explanation to it, but Altera please correct me if I am wrong.)
It would be really great to have some reliable boot debug guide/logic around this early SDM boot problems because of POR/Power, so we could proceed faster in design bring-up.
Kind regards,
Peter
Farabi_AlteraRegular Contributor
Hello Asif, Peter,
Summary
1- This is specific board issue, other board can boot up successfully
2- Agilex 5 config timing diagra should looks like this : Please scope shot nCONFIG, nSTATUS, CONF_DONE
3- Please check power rails monitored by POR are all stable during power up. If one of the power rails rippled more then 3%, the board might have power delivery issue.
regards,
Farabi
- Farabi_Altera
Hello Asaf, Peter,
Do you have update?
regards,
Farabi- dpcsu_e
Hi Farabi, in our case it was 1.8V ramping up faster than 200us, adjusting softstart capacitor solved it.
