Leakage Current in MAX 10 Bank 1A (ADC Bank)
Device：10M08DCF256I7G We have connected the following voltage divider circuit to each of Bank 1A and Bank 8 of the MAX 10 device. 12 V → 10 kΩ / 3.6 kΩ voltage divider → MAX 10 input (typical voltage: 3.18 V) The measured voltages at each bank are as follows: Bank 8: 3.17 V Bank 1A: 3.06 V The voltage at Bank 1A is lower than that at Bank 8. We checked the 12 V input voltage and resistor tolerances, but found no deviations large enough to account for this difference. We also found the following statements in the datasheet: ////////// The values in the table are specified for normal device operation. The values vary during device power-up. This applies for all VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, 1.35, and 1.2 V). 10 µA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed when the diode is on. Input channel leakage of ADC I/O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled or disabled. This is applicable to all Intel MAX 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices. The ADC I/O pins are in Bank 1A. ////////// Could you please confirm whether it is reasonable to conclude that this phenomenon is caused by leakage current specific to Bank 1A (the ADC bank)?Investigation of HIGH-Level Voltage Fluctuations on MAX 10 3.3 V LVTTL Output Signals
We are investigating the cause of fluctuations in the HIGH-level voltage of a 3.3 V LVTTL output signal from the MAX 10 FPGA. Device Part Number: 10M08DCF256I7G HIGH-Level Voltage: 2.8 V to 3.3 V 1.Verification of BANK Power Supply Stability We compared the BANK power supply voltage with the signal voltage and confirmed that the power supply voltage remains stable even when fluctuations occur in the signal voltage. 2.Relationship with the Connected Device (Under Investigation) Connection: MAX 10 → [3.3 V LVTTL, 8 mA] → DS90CR287 ・Changing the damping resistor from 22 Ω to 0 Ω did not affect the issue. Could you please advise us on the possible causes of this issue and any additional aspects we should investigate?
FPGA simulation and real HW behavior discrepancy
Dear Altera Quartus 18.1 sim lib could try 20.1 or newer but not sure this is due to Quartus version as it is sim lib. I am encounter an unexplainable experiment result that contradicts simulation and real HW. Background when interfacing a DQS DQ readout a IDDR with CCD sync flops are used. For these primitives, it should expected 1 + 2 and clock +ve edge should expect data push out. [A] This can simply considered as early push out but it should not act as such. With the use of "__ALTERA_STD__METASTABLE_SIM" we expected some metastable on the output. [B] Now things are more reasonable where 2 +ve clocks are expected. If we consider a full data w/o xx, things become unrecognizable. [C] The most interesting part when apply on real HW, it do produce correct data and the latencies do obeyed. altddio_in#( .intended_device_family ( "Cyclone IV E" ), .invert_input_clocks ( "ON" ), .lpm_hint ( "UNUSED" ), .lpm_type ( "altddio_in" ), .power_up_high ( "OFF" ), .width ( 8 ) )ddi_d_l( .aclr (reset), .datain (foo[7:0]), .inclock (bar[0]), .dataout_h (foobar_h[0+:8]), .dataout_l (foobar_l[0+:8]), .aset (1'b0), .inclocken (1'b1), .sclr (1'b0), .sset (1'b0) ); + altera_std_synchronizer_bundle#( .width (foobar_bw *2), .depth (2) )async_flops( .clk (clock), .reset_n (~reset), .din (foobar), .dout (foobar_ccd) );
Cyclone 4 PS Configuration Timing Parameters
Hi, I would like to know the PS Configuration Timing Parameters for the FPGA cyclone 4 family. However, there are no indication in the datasheet: https://docs.altera.com/v/u/docs/654327/cyclone-iv-device-handbook-volume-3-device-datasheet In page 1-26 (36/54), the file sends to another file (see note 1): but that leads to a 404 error: https://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf Where could I find the information I require? Thank you in advance for your assistance, Christophe
Introducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.How to make my first dollar as an FPGA engineer?
Hello Altera Community I am looking to better understand how the FPGA business works. 💵 Are there any websites, like in the wardogs movie, where people post projects to complete? or do I have to join a company to work on one of these big solutions with multiple types of engineers? I have send a project idea to the Altera contact form. Thanks in advance 🐳
Quartus 25.1std | Signal Tap Crash
Hello, I would like to ask for help. I'm programming a Cyclone V with Quartus 21.1 Standard edition. I'm trying to implement signal tap to my design. My stp file is able to compile with the .sof/.pof generation but when I go to acquire data Quartus by clicking "run analysis" keeps on crashing. I get the following problem. Problem Details Error: *** Fatal Error: Uncaught C++ Exception Module: quartus.exe Stack Trace: 0xc41c9: RaiseException + 0x89 (KERNELBASE) 0x671f: _CxxThrowException + 0x8f (VCRUNTIME140) 0x3b551: std::_Xout_of_range + 0x21 (MSVCP140) 0x56ef: std::_String_val<std::_Simple_types<char> >::_Xran + 0xf (sld_chi) 0x9682: CHI_CONTROL_NODE_STP_V6::construct_load_data + 0x2f2 (sld_chi) 0xe6be: CHI_CONTROL_NODE_STP_V6::initialize_setup_offload_cache + 0x4ee (sld_chi) 0xdac4: CHI_CONTROL_NODE_STP_V6::init_acquisition + 0x174 (sld_chi) 0x1182c: CHI_CONTROL_NODE_STP_V6::start + 0x22c (sld_chi) 0x58e5: CHI_CONTROL_NODE_STP::acquisition_thread_proc + 0x35 (sld_chi) 0x13b18: msg_thread_wrapper + 0x78 (CCL_MSG) 0x15f13: mem_thread_wrapper + 0x73 (ccl_mem) 0x2773: thr_thread_begin + 0x33 (ccl_thr) 0x2cd86: BaseThreadInitThunk + 0x16 (KERNEL32) 0xacaeb: RtlUserThreadStart + 0x2b (ntdll) End-trace Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Standard Edition Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 10 OS version: 10.0 Quartus Prime Information Address bits: 64 Version: 25.1std.0 Build: 1129 Edition: Standard Edition I can't seem to get to the bottom of why this is happening. I don't believe there are any Quartus patches for signal tap for version 25.1std.0 If someone could help that would be greatly appreciated.
Schematics/layout for TerasIC SoCKit rev. D with Cyclone V
Greetings! I am working with an ALTERA/TerasIC SoCKit development board for Cyclone V. I've downloaded the "SoCKit CD-ROM ( rev. D Hardware )" archive from www.terasic.com.tw, but it does not contain schematics or PCB layout files. What I want to do is access ~8 GPIO pins on the board, but it does not have a GPIO header. So I can either solder to the mysterious "AD-DA HDR" connector plus some LEDs/switches, or connect to one of the 3 groups of pins on the wide HSMC (one has 20 differential pairs, the other two have 60 pins each) using a Samtek connector. To do that, I need to know how the pins on the SoCKit's PCB connectors map to the 5CSXFC6D6F31C6 IC's pads. BTW, I really appreciate the board having pads for an Altera JTAG connector pads: EthernetBlaster can be used with it! --A.
