URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh Chavan
Regarding the Footprint creation of AGFB022R24C2E2V
Hi For the AGFB022R24C2E2V The package drawing specifies a solder resist opening of Ø0.50 ± 0.02 mm, but it does not specify the recommended PCB pad diameter. Could you please provide the recommended PCB land pattern, including the copper pad diameter and whether the pads should be solder mask defined (SMD) or non-solder mask defined (NSMD)? Addition please provide the Allegro footprint for AGFB022R24C2E2V
ModelSim-Intel FPGA Starter Edition 18.1 exits with code 211 when pressing Restart button
Hello, I am using ModelSim-Intel FPGA Starter Edition included with Quartus Prime Lite Edition 18.1. When I press the Restart button in the ModelSim GUI after running RTL simulation, ModelSim exits with the following message: "ModelSim is exiting with code 211. Check the transcript file for more information on the fatal error." Environment: - Quartus Prime Lite Edition 18.1 - ModelSim-Intel FPGA Starter Edition 18.1 - Windows PC - ModelSim path: C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem 確認したこと: - Quartus / ModelSim は再インストールされました。 - 環境変数とPATH設定を確認しました。 - 同じプロジェクトが別のPCで正しく再起動できる場合。 - このPCではGUIの再起動ボタンを押すと問題が発生します。 - PCにはTrend Micro Apex Oneがインストールされています。 - リアルタイムスキャンからIntel FPGA / ModelSimフォルダを除外した後、ModelSimは正しく動作しました。 質問: GUIの再起動ボタンを使う場合、ModelSim-Intel FPGA Starter Edition 18.1で既知の問題として、終了コード211はありますか? また、この問題はウイルス対策ソフトやエンドポイントセキュリティソフトに関係している可能性はありますか? この問題に対するおすすめの設定や回避策はありますか? ありがとうございます。
A3C* BSDL updates available?
Hello, There are several of the A3CZ, A3CU and A3CV* families which are fail compilation with syntax errors on pins duplicated (usually K24 and K25). and then a most have errors in their use of port_grouping. Are there updates available? Regars, Tom iBSDL - Intellitech BSDL Compiler Version 14.25 Copyright (C) 1993-2026 Intellitech Corp. All rights reserved. ERROR: Device package pin mappings: Duplicate pin id K24 ( IEEE Std 1149.1 Rule B.8.7.3 a). ERROR: Device package pin mappings: Duplicate pin id K25 ( IEEE Std 1149.1 Rule B.8.7.3 a). INFO: Associated Port REFCLK_GTSL1A_RX_n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH3n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH2n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH0n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH1n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden ERROR: Associated port GTSL1A_TX_CH3n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH3n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH2n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH2n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH1n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH1n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH0n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH0n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) The compile failed.
Licence in Altera 2 Complete Design Suite version 13.0 SP1 For cyclone 1
"I am using Quartus II 13.0 Subscription Edition to compile code for a Cyclone I device (EP1C3T100C8). While the build compiles successfully, the software does not generate the .sof file needed to create a .jic file. Since this device family might have limited support, does anyone know how to enable or generate the .sof file in this version?"Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA?
Hi, I am building on top of the Agilex 5E GSRD design. My goal is not to use the HPS-side DDR for the FPGA accelerator data buffer. Instead, I want the data path to be: ARM/HPS writes input data -> HPS2FPGA bridge -> FPGA-side DDR4 via EMIF_IO96B_DDR4COMP FPGA IP reads input data from FPGA-side DDR4 FPGA. IP computes and writes result back to FPGA-side DDR4 ARM/HPS reads result back from FPGA-side DDR4 via HPS2FPGA My current Platform Designer connection is roughly: HPS hps2fpga master -> EMIF_IO96B_DDR4COMP AXI memory-mapped slave FPGA accelerator memory port -> same EMIF_IO96B_DDR4COMP EMIF pins -> external DDR4 The EMIF configuration and DDR4 pin assignments are matched carefully against the example design: /agilex5e_installer_package/examples/bts_emif/bts_ddr4_2b downloaded from the agilex5e installer package. I also tested the original bts_ddr4_2b style flow in the example using: JTAG -> pattern adaptor -> EMIF -> DDR4 and DDR4 read/write tests pass without errors. So the FPGA-side EMIF DDR4 calibration/pattern test appears to work. However, when I try to access the same FPGA-side DDR4 from Linux on HPS through the HPS2FPGA bridge using devmem2, the access fails badly. For example, accessing the HPS2FPGA mapped address causes a bus error / fatal SError. One example log: root@agilex5dka5e065bb32aes1:~# devmem2 0x40000000 w /dev/mem opened. [ 1017.877669] SError Interrupt on CPU2, code 0x00000000be000011 -- SError [ 1017.877707] CPU: 2 PID: 791 Comm: devmem2 Not tainted 6.12.19-altera-g7b497655d942 #1 [ 1017.877717] Hardware name: SoCFPGA Agilex5 SoCDK (DT) ... [ 1017.877814] Kernel panic - not syncing: Asynchronous SError Interrupt ... Bus error For comparison, I connected the same HPS2FPGA bridge to an on-chip memory in the FPGA fabric. Accessing that on-chip memory from HPS with devmem2 works correctly. So the HPS2FPGA bridge itself seems functional. Current observations: HPS2FPGA -> on-chip memory works. JTAG -> pattern adaptor -> EMIF -> DDR4 works. EMIF calibration appears to pass. HPS2FPGA -> EMIF DDR4 causes SError / bus error / Linux kernel panic. Here is my current Platform Designer connection. In the screenshot, you can see that I copied over the EMIF-driving logic from the installer package. For emif_axi4, one connection goes to my IP’s memory port, and the other goes to the HPS hps2fpga interface, although that HPS connection is not shown in this screenshot. Does anyone have any clues about what might be wrong here? Is this expected to work, or is this use case currently not supported, i.e. HPS reading/writing data directly to FPGA-side DDR through HPS2FPGA while an FPGA IP also accesses the same DDR through the EMIF AXI4 interface? If any additional files would be helpful, I can provide them. Thank you in advance!Max 10 Device Migration from SA auf SC
Is it possible to migrate from an SA to an SC device when I not use the ADC I found this Thread https://community.altera.com/discussions/fpga-device/max10-sideways-migration/264028 But what is not mentioned that some pins are other Connected For example, U169 package: D3 Sa: ADC_Ref; SC: VCCA3 D2 SA: ANAIN1; SC: GND It seems this case is not supported in the Pin Migration. Is there some document which explains which pins are different or must I check each of the 169 pins individual? And can I Left open the “dual used pins” or must I provide Jumper to switch between both variances? Kind Regards Jonas
Agilex 7 (F-tile/R-tile) PCIe Gen5 RX Compliance Test Issue -some lanes can't enter Loopback
Hi Teams, We are currently working on a custom PCIe Add-in Card based on Agilex 7 (F-tile / R-tile). Note that the FPGA firmware is provided to us by our end customer. Design Context: According to our customer, the provided FPGA firmware utilizes a PCIe Endpoint ROM, which includes a built-in function to handle the transition into loopback mode. The customer believes this loopback mechanism should function properly. Current Status: PCIe Gen5 TX Compliance Test: Passed successfully. PCIe Gen5 RX Compliance Test: Encountered issues during our recent testing at an external lab. Problem Description: During the Rx test, we observed that lanes 0, 1, 7, and 15 successfully entered loopback mode and passed. However, the remaining lanes (Lanes 2-6 and 8-14) could not be initiated or triggered into loopback mode by the BERT. According to the lab's experience, this type of issue usually requires a specific or test-oriented FPGA firmware version (such as a special configuration for LTSSM or compliance mode) to properly conduct the PCIe Rx compliance test across all lanes. Our Questions: Does the built-in PCIe Endpoint ROM loopback function in Agilex 7 F-tile/R-tile require physical Lane 0 to be active in order to trigger loopback on other lanes? Since the test lab uses a 1-lane or 2-lane BERT and moves the lanes sequentially (meaning Lane 0 will be in Electrical Idle when testing Lane 2/3), will this cause the EP ROM's state machine to hang or ignore the BERT's TS1/TS2 loopback commands? Are there any known limitations, workarounds, or specific IP parameters we need to modify to allow individual lane loopback entry without relying on Lane 0? Any insights or suggestions would be greatly appreciated, as we need to sync this back to our customer's firmware team. Thanks!
