Updated .brd file for Stratix 10 GX dev kit
Referencing this post: EK-10M08E144 PCB .brd file corrupted | Altera Community - 302242 The .brd file that comes in the documentation at: https://www.altera.com/products/devkit/po-3028/stratix-10-gx-signal-integrity-development-kit-h-tile ...was done in Allegro, prior to version 16.6. The only available Allegro viewer gives an error because it was done prior to version 16.6, and you need the DB Doctor utility to update the file. The only way to get the DB Doctor utility is to install Allegro. If I had Allegro...I would not be installing the Allegro viewer. Altera: As mentioned in the post above (well over a year ago), it would make sense for you to update your files so customers can view the board of their $10K+ development board. How do we make that happen? Thanks!
Subject: Hitless Update Implementation Guidelines (AN904)
Target Devices: 10M08SAU324I7G / 10M25SAU324I7G Reference Document: AN904: MAX 10 Hitless Update Implementation Guidelines KDB 000080468 https://community.altera.com/discussions/fpga-device/subject-issues-implementing-hitless-update-on-max-10-via-quartus-prime-programme/355534/replies/355841?emcs_t=S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufE1TNzJGWlhLRUhRVlowfC0xfFNVQlNDUklQVElPTlN8aEs Problem Description: Hi Altera Team, Thank you for the detailed explanation. I apologize for the delayed response, as I took some time to run experiments based on your feedback. After completing my implementation testing, I would like to clarify a few points: 1. Clarification on Section 1.5 in AN904 Section 1.5 of AN904 is titled "1.5. Hitless Update using Intel Quartus Prime Programmer". However, since your response indicates that the Quartus Prime Programmer GUI itself cannot achieve a true hitless update during reconfiguration without logic/IO interruption, the section title seems misleading. Could you confirm if Section 1.5 is actually intended to describe using the Quartus Prime Programmer to generate .jbc, .jam files for external hitless execution, rather than executing the update directly via the Programmer GUI? 2. JBC Hitless Update Issue Following KDB 000080468 I generated a .jbc file by strictly following the workflow outlined in KDB 000080468: During execution, hitless update still fails (I/O states drop/reset during reconfiguration). However, after rebooting/power-cycling the CPLD, the new FW/image runs successfully. Could you help verify: • Is there any step missing in my .jbc generation flow based on KDB 000080468? • If the generation sequence is correct, which part of the execution flow (e.g., Jam Player ACTION parameter, TAP Reset timing, or clamp release sequence) could cause the I/O clamping to fail prematurely? 3. Support for Partial / CFM0-Only Hitless Update Is it supported to perform a Hitless Update when programming only CFM0 (ROM0) instead of the full flash image? Does the ISP Clamp and Boundary-Scan mechanism function the same way during a partial image update? Thanks and best regards,
Quartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound
Hello Altera Community, I am working on an FPGA project using a Cyclone IV FPGA development board and an Altera USB-Blaster. I am currently unable to program the FPGA because Quartus Programmer cannot access the JTAG server. System details: - OS: Windows 11 64-bit - Software: Quartus Programmer 21.1 - Installation path: C:\intelFPGA\21.1\qprogrammer - Programmer: Altera USB-Blaster - FPGA: Cyclone IV development board The USB-Blaster is detected by Windows Device Manager and the driver is installed. The USB-Blaster also powers on normally. However, Quartus Programmer gives: "Attempted to access JTAG server -- internal error code 82 occurred" When I run: jtagconfig I get: Error when scanning hardware - Server error Sometimes it also hangs at: Connecting to server(s) [...] I checked the JTAG server using: jtagserver --status It reports: Installed JTAG server is 'C:\intelFPGA\21.1\qprogrammer\bin64\jtagserver.exe' Server is stopped Remote clients are disabled I tried reinstalling the JTAG server: jtagserver --install jtagserver --start But the server immediately stops. I also tried: net start "Altera JTAG Server" The result was: The Altera JTAG Server service could not be started. The service did not report an error. NET HELPMSG 3534. I then ran: jtagserver.exe --foreground and received: Unable to bind changedetect socket: 10048 Can't bind to TCP port 1309 - exiting I checked the port using: netstat -ano | findstr 1309 and found that TCP port 1309 was being used/listened to by another process, for example PID 12888. I tried terminating the process using: taskkill /F /PID 12888 but Windows reported: ERROR: The process with PID 12888 could not be terminated. Reason: There is no running instance of the task. I also tried stopping the JTAG server, reinstalling it, and restarting it. In addition, I already tried the following: 1. Disabled PCI Express → Link State Power Management. 2. Disabled USB Root Hub power saving ("Allow the computer to turn off this device to save power"). 3. Stopped the Print Spooler service. 4. Closed Quartus/Programmer-related applications. 5. Reinstalled the JTAG Server. 6. Restarted the computer. 7. Tried starting the JTAG server manually. 8. Checked TCP port 1309 using netstat. The problem still remains. My main questions are: 1. Why is Quartus Programmer 21.1 unable to start the JTAG Server? 2. What is causing TCP port 1309 to remain occupied? 3. Is there a known issue with Quartus Programmer 21.1 and Windows 11? 4. Is there a recommended patch, driver, or newer Quartus Programmer version for this problem? 5. Is it possible to configure the JTAG server to use another TCP port? 6. What is the correct way to completely remove and reinstall the JTAG Server on Windows 11? 7. Is there anything else I should check before reinstalling Quartus Programmer? I would appreciate any guidance on how to get the JTAG Server running so that jtagconfig can detect my USB-Blaster and FPGA. Thank you.
Mentor Graphics PADS-compatible footprint/library file # A5ED065BB32AI4S
Team, Our customer currently proceeding with the PCB layout design and require the FPGA footprint for the following part: Part Number: A5ED065BB32AI4S We have checked the available resources but could not find the required footprint for this device in a Mentor Graphics PADS-compatible format. Therefore, we kindly request you to provide the appropriate Mentor Graphics PADS-compatible footprint/library file for the above FPGA, along with the relevant package and pad dimensions, if available. Your support in providing the footprint at the earliest would help us proceed with the PCB layout design without delay. Regards amolkumar
Part query<45714>
Dear Team, Hope you are doing well. Can you please advise if below listed part no's are Active and available from ALTERA. I am unable to find these in website. Part no EPCQ128ASI16N EPCQ64ASI16N EP2AGX45DF29I5G EP3C80F780I7 EP3C40F780I7N Any help you provided is highly appreciated. Regards, Santosh
