Agilex 7 (F-tile/R-tile) PCIe Gen5 RX Compliance Test Issue -some lanes can't enter Loopback

Hi Teams,

We are currently working on a custom PCIe Add-in Card based on Agilex 7 (F-tile / R-tile). Note that the FPGA firmware is provided to us by our end customer.

Design Context: According to our customer, the provided FPGA firmware utilizes a PCIe Endpoint ROM, which includes a built-in function to handle the transition into loopback mode. The customer believes this loopback mechanism should function properly.

Current Status:

PCIe Gen5 TX Compliance Test: Passed successfully.

PCIe Gen5 RX Compliance Test: Encountered issues during our recent testing at an external lab.

Problem Description: During the Rx test, we observed that lanes 0, 1, 7, and 15 successfully entered loopback mode and passed. However, the remaining lanes (Lanes 2-6 and 8-14) could not be initiated or triggered into loopback mode by the BERT.

According to the lab's experience, this type of issue usually requires a specific or test-oriented FPGA firmware version (such as a special configuration for LTSSM or compliance mode) to properly conduct the PCIe Rx compliance test across all lanes.

Our Questions:

Does the built-in PCIe Endpoint ROM loopback function in Agilex 7 F-tile/R-tile require physical Lane 0 to be active in order to trigger loopback on other lanes?

Since the test lab uses a 1-lane or 2-lane BERT and moves the lanes sequentially (meaning Lane 0 will be in Electrical Idle when testing Lane 2/3), will this cause the EP ROM's state machine to hang or ignore the BERT's TS1/TS2 loopback commands?

Are there any known limitations, workarounds, or specific IP parameters we need to modify to allow individual lane loopback entry without relying on Lane 0?

Any insights or suggestions would be greatly appreciated, as we need to sync this back to our customer's firmware team. Thanks!