Agilex 5 RCOMP_GTS connection change and its effect on HVIO input pins

Great questions — let me address both directly.

Question 1: Is this a silicon/device change or just a documentation update?

This is a documentation/guideline update only — there is no change to the silicon or the device itself. Altera issued Customer Advisory ADV0057 to inform customers of the updated Pin Connection Guidelines for Agilex 5 and Agilex 3 device families. Importantly, this notification is explicitly stated to not be a device change — there are no changes to the products. ADV0057 Agilex® 3 and Agilex® 5 FPGA Devices Pin Connection Guidelines Update

The specific update in the Agilex 5 PCG was to Section 1.3.2 (GTS Transceiver Pins): the Connection Guidelines for the RCOMP_GTS pin were clarified to state that you should leave these floating only if the entire side of the GTS transceiver power supply pins (VCCEHT_GTS and VCCERT_GTS) are tied to GND. ADV0057 Agilex® 3 and Agilex® 5 FPGA Devices Pin Connection Guidelines Update

The authoritative connection requirement itself is: The RCOMP_GTS pins serve as external biasing resistors for GTS. Each RCOMP_GTS[L1,R4][A,B,C,D,E,F]_P pin must be connected with a 499-Ω resistor (±0.1%) to the corresponding RCOMP_GTS[L1,R4][A,B,C,D,E,F]_N pin. In the PCB layout, the trace from this pin to the resistor must be routed to avoid any aggressor signals. These pins may be left floating only if the entire side of the GTS transceiver power supply pins (VCCEHT_GTS and VCCERT_GTS) are tied to GND. Pin Connection Guidelines

Question 2: Why do HVIO input pins stop working when RCOMP_GTS is floating?

Your intuition that HVIO and GTS transceiver banks are separate is reasonable, but there is a specific interaction at the hardware level. In Agilex 5 (and Agilex 3) devices that include transceivers, if the board connects power to the GTS transceiver bank but leaves the RCOMP pin unconnected — regardless of whether the design actually instantiates a transceiver — HVIO pins configured as input or bidirectional in a specific HVIO bank may fail to function after device configuration. The pins can appear stuck at high, not respond to user logic, or fail to transition to the expected I/O behavior. This does not affect the device configuration process and the device does enter user mode. Critically, the issue specifically affects the HVIO bank adjacent to the GTS transceiver bank, and is related to specific power and pin connection conditions during board design. Why do HVIO pins in an Agilex® 5 or Agilex® 3 FPGA HVIO bank appear to be non-functional after device configuration?

There is also a related Quartus Prime Pro software-side manifestation of this issue: due to a problem in Quartus Prime Pro Edition Software versions 23.4.0 Patch 009, 23.4.1, and 24.1, the HVIO input pin may be stuck at high in Agilex 5 designs that do not include a transceiver and leave the RCOMP pin unconnected when the HVIO pin is configured as input or bidirectional. The device configuration process itself is not affected. A patch is available for version 24.1 (Windows: quartus-24.1-0.15fw-windows.exe; Linux: quartus-24.1-0.15fw-linux.run). Why does the high-voltage I/O (HVIO) input pin stuck at high in Agilex™ 5 FPGA devices?

Bottom line for your board design: Always connect the RCOMP_GTS P/N pins with the 499-Ω (±0.1%) resistor whenever the GTS transceiver power rails (VCCEHT_GTS / VCCERT_GTS) are powered — even if you are not using transceivers in your design. Omitting this connection while the GTS power rails are active is what triggers the HVIO failure in the adjacent bank.

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Thank you very much.