Forum Discussion
New ContributorAgilex 5 RCOMP_GTS connection change and its effect on HVIO input pins
New ContributorThank you for the explanation. I understand that this is a documentation update rather than a silicon change, and that RCOMP_GTS must be connected as specified when the corresponding GTS power supplies are powered.
However, my second question concerns the underlying internal mechanism, rather than the failure conditions or workaround.
Could you please clarify the following?
- What internal architectural dependency exists between the GTS transceiver bank and the adjacent HVIO bank?
- Even when no transceiver is instantiated in the design, why does leaving RCOMP_GTS floating prevent the HVIO input or bidirectional pins from being configured correctly?
- Why is the impact limited to the adjacent HVIO bank?
If detailed circuit information cannot be disclosed, a high-level explanation would be sufficient.
Thank you.
Regular ContributorHi Mario,
Altera does not publish a detailed internal circuit description of the GTS-to-HVIO path. At the level we can share publicly: this is a product architecture requirement on Agilex 5 and Agilex 3 devices with GTS. When RCOMP_GTS on a side is left floating and that side's GTS supplies are powered, the HVIO pins in the HVIO bank adjacent to that GTS bank are not configured correctly during device configuration. The device still configures and enters user mode, but those HVIO pins (input or bidirectional) can look stuck high or otherwise non-functional.
That is also why:
- Instantiating no transceiver in the Quartus design does not avoid the issue. The board power / RCOMP connection condition is what matters.
- The impact is limited to the HVIO bank adjacent to the affected GTS side, as stated in the Knowledge Base article.
- mario
Hi,
Thank you for your reply.
I understand that the detailed internal circuit architecture is not publicly available.
We are planning to follow the KDB guidance and connect a 499 Ω resistor between the RCOMP_GTS P and N pins.Could you please also clarify the following two points?
- What is the maximum voltage across this resistor? We do not expect an issue with its voltage rating or derating, but would like to confirm this as a precaution.
- Are there any constraints or recommendations regarding the resistor placement or the trace length between the RCOMP_GTS pins and the resistor?
Thank you.
