Steve-Mowbray-ENL
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Re: How to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?
Hi Aqid Thanks -- all understood -- my purpose is to identify why timing analyser reports CLKUSR at 125MHz when our design requires 100MHz -- and if there is a method to indicate to Quartus/Platform-Designer what CLKUSR frequency actually is or failing that if the incorrect CLKUSR frequency reported is in fact unimportant and can be ignored (our project does seem to mostly run as expected but there are some quirks which could be related to transceiver operation) Regards, SteveRe: How to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?
Hi Farabi Rather than experimenting with cludge fixes I am focussing on the Platform Designer automatic generated: (*altera_attribute = "-name SDC_STATEMENT \"if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] }\"" *) associated with the transceiver reset sequencer instance in the design -- doesn't seem to be an obvious IP parameter to tell the instance that CLKUSR is at 100MHz rather than 125MHz... Regards, SteveRe: How to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?
Thanks Frank -- yes that is my understanding -- my concern is by explicitly assigning the CLKUSR pin does Quartus infer that the pin is now a GPIO pin thus excluding transceiver use -- doing a project build now so will hopefully have some Quartus reporting to discuss shortly. Regards Steve UPDATE: build complete with interesting critical warning: Critical Warning (18326): The design pin 'clkusr' has been assigned to CLKUSR pin location 'Y15'. Quartus Prime auto-reserves the CLKUSR pin for calibration of transceivers and certain IOs. If the pin 'clkusr' will not be assigned a 100-125MHz clock, you must remove the location assignment on it. Otherwise, to remove the critical warning use the QSF assignment 'set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF'. So optimistic interpretation of the above implies that so long as clkusr pin has valid clock signal then transceivers will still calibrate correctly even when the global assignment is applied to suppress the critical warning... Digging through the Platform Designer synthesis files I found: (*altera_attribute = "-name SDC_STATEMENT \"if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] }\"" *) in "altera_a10_xcvr_reset_sequencer_211\synth\alt_sld_fab_altera_a10_xcvr_reset_sequencer_211_33t7nri.v"Re: How to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?
Thanks Frank -- seems straightforward -- couple of questions before I fire up quartus -- is there any consequences for being explicit on this pin -- also any chance this clock is useable in the user logic as this would be useful "free" clock source?How to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?
Timing analyser reports CLKUSR at 125MHz but target system has 100MHz on this pin to accommodate AS in combination with transceiver calibration as per the manuals -- there doesn't seem to be any consequences as the project seems to run fine but is a bit unsettlingRe: Using PCIe HIP core clock out to drive IOPLL reference clock -- advise on set_false_path syntax
Hi FvM Yes agreed which is why I am out of my depth here -- there are no data paths between the 125MHz and 100MHz domains -- previously the 100MHz domain had its own dedicated crystal as shown below: In the external crystal configuration the project makes timing comfortably however the extra crystal has been removed from the design and using the PCIe core clock out as its substitute causes build timing to collapse... I note that PCIe core clock out appears to be spread spectrum for Arria 10 devices when measured on external pin which is great for EMC but perhaps is causing the fitter/timing-analyser difficulties? If solution is not to set a false path how do I tell Quartus to be relaxed about using core clock out as reference clock to the IOPLL instance? Regards SteveUsing PCIe HIP core clock out to drive IOPLL reference clock -- advise on set_false_path syntax
Hi Need advise on suitable set_false_path design constraint construction for the following scenario where PCIE HIP core clock out is used as the reference for an IOPLL instance: Impact of doing this is fitter takes much longer and result fails timing by a big margin so I am guessing a design constraint false path is required... My initial attempt at setting a false path set_false_path -from [get_clocks {u0|pcie_hip|coreclkout_hip}] -to [get_clocks {u0|iopll_1|refclk}] reports <from> and <to> arguments are empty collections I would be grateful for any guidance -- apologies for outright asking for someone to show me how to do this but I'm finding SDC file content and usage quite impenetrable... Thanks Steve
