Steve-Mowbray-ENL
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Re: Using PCIe HIP core clock out to drive IOPLL reference clock -- advise on set_false_path syntax
Hi FvM Yes agreed which is why I am out of my depth here -- there are no data paths between the 125MHz and 100MHz domains -- previously the 100MHz domain had its own dedicated crystal as shown below: In the external crystal configuration the project makes timing comfortably however the extra crystal has been removed from the design and using the PCIe core clock out as its substitute causes build timing to collapse... I note that PCIe core clock out appears to be spread spectrum for Arria 10 devices when measured on external pin which is great for EMC but perhaps is causing the fitter/timing-analyser difficulties? If solution is not to set a false path how do I tell Quartus to be relaxed about using core clock out as reference clock to the IOPLL instance? Regards SteveUsing PCIe HIP core clock out to drive IOPLL reference clock -- advise on set_false_path syntax
Hi Need advise on suitable set_false_path design constraint construction for the following scenario where PCIE HIP core clock out is used as the reference for an IOPLL instance: Impact of doing this is fitter takes much longer and result fails timing by a big margin so I am guessing a design constraint false path is required... My initial attempt at setting a false path set_false_path -from [get_clocks {u0|pcie_hip|coreclkout_hip}] -to [get_clocks {u0|iopll_1|refclk}] reports <from> and <to> arguments are empty collections I would be grateful for any guidance -- apologies for outright asking for someone to show me how to do this but I'm finding SDC file content and usage quite impenetrable... Thanks Steve
