Forum Discussion

Steve-Mowbray-ENL's avatar
Steve-Mowbray-ENL
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

FPGA passive serial configuration -- detect as PCIe device in Linux after configuration

Hi In passive serial configuration the Linux platform powers on and is booted with FPGA in unconfigured state -- our RBF file is then configured via passive serial and working but is not detected as...
Configuration
  • Wincent_Altera's avatar
    Wincent_Altera
    1 year ago

    Hi Steve,

    Thanks for your confirmation, I will transition this support thread to community.
    I saw corestar have reply some workaround, perhaps you may refer to that and see if that able to help you or not.

    Any time in future, if you having any problem, you may file a new thread.
    Someone will be there to support you. If you need my support on PCIe IP, please mention my name "Wincent" so that this will route to my support Q.

    If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me via this forum page of the cause so that I can learn from it and strive to enhance the quality of future service experiences.

    Regards,

    Wincent_Altera

    p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.

  • Steve-Mowbray-ENL's avatar
    Steve-Mowbray-ENL
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi Wincent

    I dont see any Linux guidance related to the above link -- specifically it is the Linux steps required to get the PCIe endpoint correctly detected in the Linux PCIe master device after passive serial configuration that we need

    Regards

    Steve

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      1 year ago

      Hi Steve,

      I am supporting PCIe IP area, based on your reply.
      I believe you try to convert the Programming Files RBF into passive serial configuration in order to run the design , am I get this right ?
      This is out of my support area actually, however I can try my best to assist

      In order to successful run the passive serial file please check below guide
      https://cdrdv2-public.intel.com/705024/ug-qpp-programmer-19-3-683039-705024.pdf

      1. Can you try to use JTAG mode and see if it can be configure successfully?

      2. If in JTAG mode it can be configure successfully, it can be something is wrong with the connection on board or flash. Do you follow the pin connection guidelines? https://www.intel.com/content/www/us/en/docs/programmable/683814/current/intel-arria-10-gx-gt-and-sx-device-family.html

      3. How is the MSEL setting?


      Hope my suggestion able to help you to move a step forward, Please accept my apology that this is out of my support area.
      IF your issue is still unable to solve, I suggest to file a new forum thread with title example "Arria 10: Passive Serial Configuration-programming failure" . So that our configuration team support specialist is able to look at this.

      Let me know if you have different thoughts.

      Regards,
      Wincent

      • FvM's avatar
        FvM
        Icon for Super Contributor rankSuper Contributor
        1 year ago
        Hi,
        not sure if the observed problem is failed configuration or only missing PCIe device enumeration by PC Bios. In the latter case, the problem may be simply too late configuration. Depending on Bios behaviour, rescan doesn't necessarily help, a reboot may be necessary.