not able to detect any instance for core < hps_sdram_p0 >

Hi,

I'm trying to get into a Cyclone V based evaluation board (EBV SoCrates). While already getting LEDs to blink, on pure FPGA side, now I wanted to do a setup with QSYS. I took the "default clock", a "hard processor system" and created a "custom" component to combine it with one of my vhdl files. Another VHDL file is not in the QSYS setup. I compiled the QSYS and I integrated the resulting .qip into the project, together with the other .vhdl file.

Finally, I adjusted the toplevel VHDL file, but there seems to be something missing. After setting the LED pins and one clock pin (the same I used before). At compilation then, I get the following:

--- Quote Start ---

Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/altera_reset_controller.sdc'

Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/hps_sdram_p0.sdc'

Info (332151): Clock uncertainty is not calculated until you update the timing netlist.

Error: The auto-constraining script was not able to detect any instance for core < hps_sdram_p0 >

Error: Verify the following:

Error: The core < hps_sdram_p0 > is instantiated within another component (wrapper)

Error: The core is not the top-level of the project

Error: The memory interface pins are exported to the top-level of the project

--- Quote End ---

What is wrong here? What is meant by "hps_sdram_p0", I did not write a component by this name - where can I look this up?

I tried to verify the items, but I'm completely unsure. How can I check if hps_sdram_p0 is instantiated within another component?

The .qip (supposed it is meant by "core"), is definitely not the toplevel. I assume the "memory interface pins" as main cause, since I did not set anything here. But - which memory inteface pins, do I need? Where to look up what is required, in order to check its address in the processor's datasheet??!