How do I address known software issues for Stratix® V FPGA, Arria® V FPGA, and Cyclone® V FPGA devices in the Quartus II software version 12.0 SP2?
Description There is a single patch available to address known software issues for Stratix® V FPGA, Arria® V FPGA, and Cyclone® V FPGA devices in the Quartus® II software version 12.0 SP2. This patch will be updated periodically with the latest software fixes. Check here periodically for updated files. You can refer to the readme file for the date the file was updated and a list of software fixes. Resolution Download and install the Stratix V/Arria V/Cyclone V FPGA device patch 2.dp10 from the appropriate link below. You must install the Quartus II software version 12.0 SP2 before installing this patch. Note that you should not install any non-Stratix V/Arria V/Cyclone V FPGA patches on the Quartus II software version 12.0 SP2 after installing this patch. Patch 2.dp10 includes all the fixes from previously-released patches 2.dp2, 2.dp3, 2.dp4, 2.dp5, 2.dp6, 2.dp7, 2.dp8 and 2.dp9. You can install patch 2.dp10 over previous device patches, but you do not need to install previous device patches before installing 2.dp10. Download the version 12.0 SP2 patch 2.dp10 for Windows (.exe) Download the version 12.0 SP2 patch 2.dp10 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.dp10 (.txt) To install a previously-released version of the Quartus II software version 12.0 SP2 Stratix V/Arria V/Cyclone V device patch, select the appropriate link below. Device patch 2.dp9 Download the version 12.0 SP2 patch 2.dp9 for Windows (.exe) Download the version 12.0 SP2 patch 2.dp9 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.dp9 (.txt) Device patch 2.dp8 Download the version 12.0 SP2 patch 2.dp8 for Windows (.exe) Download the version 12.0 SP2 patch 2.dp8 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.dp8 (.txt) Device patch 2.dp7 Download the version 12.0 SP2 patch 2.dp7 for Windows (.exe) Download the version 12.0 SP2 patch 2.dp7 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.dp7 (.txt) Device patch 2.dp6 Download the version 12.0 SP2 patch 2.dp6 for Windows (.exe) Download the version 12.0 SP2 patch 2.dp6 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.dp6 (.txt) Device patch 2.dp5 Download the version 12.0 SP2 patch 2.dp5 for Windows (.exe) Download the version 12.0 SP2 patch 2.dp5 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.dp5 (.txt) Device patch 2.dp4 Download the version 12.0 SP2 patch 2.dp4 for Windows (.exe) Download the version 12.0 SP2 patch 2.dp4 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.dp4 (.txt) Device patch 2.dp3 Download the version 12.0 SP2 patch 2.dp3 for Windows (.exe) Download the version 12.0 SP2 patch 2.dp3 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.dp3 (.txt) Device patch 2.dp2 Download the version 12.0 SP2 patch 2.dp2 for Windows (.exe) Download the version 12.0 SP2 patch 2.dp2 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.dp2 (.txt) Related Articles How do I generate programming files for Arria V D7, B7, and B5 devices in the Quartus II software version 12.0 SP2? Why does Design Space Explorer only show two effort levels for performance optimization? Internal Error: Sub-system: ASMGX, File: /quartus/comp/asmgx/asmgx_stratixv.cpp, Line: 480 Why might my Stratix V PCIe Gen 2 design intermittently downtrain to Gen1 speed? Internal Error: Sub-system: ASM, File: /quartus/comp/asm/asm_bit_connect.cpp, Line: 494 *** Fatal Error: Stack Overflow, TIS_RE_DELAY_TREE_TRANSIENT_NODE Why do reads from my Altera PLL Reconfig megafunction fail? Why do I see different fitting and timing results when I recompile my design in the Quartus II software version 12.0 SP2 and earlier?Why does a design with a TX and RX Soft-CDR LVDS SERDES assigned to the same bank in an Intel® Arria® 10 device fail to fit?
Description Due to a bug in the Quartus® II software, a design that has LVDS SERDES IP core configured in TX mode and RX Soft-CDR mode assigned to the same I/O bank in an Intel® Arria® 10 device will fail at the fitter stage. This is because the phase-locked loop (PLL) instances within the two IP cores will not be correctly merged by the Quartus® II software. Therefore different PLLs will be required for the different LVDS SERDES IP cores. Each I/O bank has only one I/O PLL though. This problem only affects the RX Soft-CDR configuration. RX Non-DPA or RX DPA-FIFO configurations are not affected. Note that the Triple Speed Ethernet IP core uses LVDS SERDES IP configured in RX Soft-CDR mode. Resolution Download the following patch for version 14.0 Intel Arria 10 FPGA Edition of the Quartus® II software: Version 14.0a10 patch 0.01a for Windows (.exe) Version 14.0a10 patch 0.01a for Linux (.run) Version 14.0a10 patch 0.01a readme file (.txt) This problem is fixed starting with the Quartus® II software version 14.1.Why can't I download design examples in AN367?
Description Download the application note AN 367: Implementing PLL Reconfiguration in Stratix II Devices below. Page 31 mentions a design example #3 titled < Implementing Phase Shift Stepping Using the ALTPLL_RECONFIG Design with Write Parameters>. There is no link to this design example. Resolution You can download the design examples from this link: Design files for Application Note AN367. Related Articles AN 367: Implementing PLL Reconfiguration in Stratix II DevicesWhy is there a voltage drop in single-ended I/O standards when located on dedicated differential input pins on side I/O banks in Stratix® III devices for designs compiled in the Quartus® II software v8.0?
Description The Quartus® II Software v8.0 incorrectly enables an internal resistor between two I/Os of a side bank dedicated differential input pair when each I/O is configured as single-ended and any of the following conditions are true: The current strength is not specified The input parallel on chip termination (OCT) option for the I/O is enabled The output series OCT option for the I/O is enabled This problem affects only Stratix® III devices. If both I/Os in this pair are input-only, the internal resistor is enabled incorrectly only if the input parallel termination option for either input is enabled. This resistor may cause the I/O pin to malfunction when it is single-ended by reducing the complementary pin voltage. Resolution This problem is fixed beginning with the Quartus® II software v8.0 SP1. Get the latest service pack from the Download Center. To correct this problem in the Quartus II Software v8.0, if you cannot upgrade to the latest service pack version, download and install patch 0.22 below.External I/O Channels Unavailable in Custom Platforms Ported from the Altera Stratix V Network Reference Platform
Description When designing your Custom Platform from the Stratix ® V Network Reference Platform (s5_net), if you perform the base revision compilation using a kernel that does not exercise all available I/O channels, all unused I/O channels will be excluded in the resulting kernel partition interface, and will be inaccessible to all subsequent board designs. Resolution When creating your Custom Platform from s5_net, perform all compilations using kernels that exercise all available I/O channels.Error: WDC_PCiScanDevices failed.
Description Attempting to configure a board with reprogram.exe might fail with the message: WDC_PCiScanDevices failed. Error 0x2000000f - Device not found Error opening the device This error might result from the following causes: The board is missing a default configuration image. The board does not finish configuring the FPGA until after the system enumerates all of its PCI Express® (PCIe®) devices. Resolution If the board is missing a default configuration image, update or change the default configuration image (also referred to as a programming file, .sof or .rbf). Refer to the board manufacturer\'s documentation for more information. If your board has been set up with a default programming file but does not appear in your operating system\'s list of devices, perform the following tasks: On the first system boot after the FPGA board has been powered down, perform a soft reboot (that is, reboot the host operating system without removing power to the PCIe devices). If a soft reboot does not resolve the problem and you have a system that allows you to configure the BIOS to increase the delay before the system performs PCIe device enumeration, set the delay to a higher value to provide more time for the board to configure the FPGA. If performing a soft reboot and increasing the delay value do not resolve the problem, most systems allow you to pause the boot sequence by entering the BIOS setup menu and then exit without saving changes. This pause gives the board enough time to configure the FPGA after power-up, and then restarts the boot sequence, re-enumerating the PCIe devices.Why does my synthesis fail on the floating-point library blocks?
Description Synthesis may fail with designs that include floating point library blocks. This issue affects all designs that use floating-point library blocks. The design fails. Resolution To work around the issue, perform the following steps: In the import directory that DSP Builder creates (DSPBuilder_<modelname>_import), when you compile (which fails), create a file called aaa_add.tcl (alphabetically first so it runs before other files). Add the following lines to that file: set quartus_dir $::env(QUARTUS_ROOTDIR) if [info exists ::env(DSPBA_HDL_DIR)] { set dspba_hdl_dir $::env(DSPBA_HDL_DIR) } else { set dspba_hdl_dir /dspba/Libraries } set_global_assignment -name VHDL_FILE /vhdl/fpc/hcc_package.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/math_package.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/hcc_implementation.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/math_implementation.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/fpc_library_package.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/fpc_library.vhd Create another file called aaa_add_msim.tcl. Add the following lines: set base_dir "<path to your DSPBA rtl directory>" set quartus_dir $::env(QUARTUS_ROOTDIR) if [info exists ::env(DSPBA_HDL_DIR)] { set dspba_hdl_dir $::env(DSPBA_HDL_DIR) } else { set dspba_hdl_dir /dspba/Libraries } file delete -force /fpc vlib fpc vmap fpc /fpc vcom -quiet -93 -work /fpc "/vhdl/fpc/hcc_package.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/math_package.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/hcc_implementation.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/math_implementation.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/fpc_library_package.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/fpc_library.vhd" Rerun the complation. This problem is fixed in DSP Builder v13.1.Chainin and Chainout Ports in Arria 10 Native Fixed Point DSP IP Core Not Supported for m18x18_full Operation Mode.
Description When the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode, the chainin and chainout ports are visible to users. However, these ports are disabled internally in m18x18_full operation mode. If you connect the chainin and chainout ports when the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode, there will be no data transfer in and out to the DSP core. Resolution Leave the chainin and chainout ports unconnected when the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode. This issue will be fixed in a future version of the Quartus II software.Assign LVDS I/O standard-supported pins in right I/O banks of Arria V A1/A3/C3 devices as PLL clock input pins only
Description If you use the Quartus II software version 13.0 DP2 or 13.0 SP1 to create a design that targets an Arria V A1, A3 or C3 device, and you use the LVDS I/O standard-enabled pins in the right I/O bank for purposes other than as phase-locked loop (PLL) clock input pins, the resulting FPGA hardware might not function properly. Resolution You must assign the LVDS I/O standard-enabled pins in the right I/O bank as PLL clock input pins only. The Quartus II software version 13.0 DP2 or 13.0 SP1 does not issue an error message for incorrect assignments to these LVDS I/O standard-enabled pins.L2 Cache Controller Revision Incorrectly Listed as r3p2
Description The Cortex-A9 Microprocessor Unit Subsystem chapter in Volume 3: Hard Processor System Technical Reference Manual of the Arria V Device Handbook and the Cyclone V Device Handbook incorrectly reports the revision number of the ARM CoreLink Level 2 Cache Controller L2C-310. This chapter reports the L2 cache controller revision as r3p2. The actual revision number of the L2 cache controller in these devices is r3p3. Resolution Update to v14.0 or later of the handbook. If you are looking at an earlier handbook, disregard the listed revision number.