What is the maximum downward pressure that can be applied to the top of Intel® FPGA BGA packages?
Description The following guidelines refer to the downward pressure or compressive load that can be applied to the top of Intel® FPGA BGA packages: For packages with eutectic SnPb (tin-lead) balls, use the following constant compressive loads: - 3g per solder ball for 0.5mm pitch MBGA package - 6g per solder ball for 0.8mm pitch UBGA package - 7g per solder ball for 0.92mm hex pitch FBGA package - 8g per solder ball for 1.00mm hex pitch FBGA package - 8g per solder ball for 1.00mm pitch FBGA package - 12g per solder ball for 1.27mm pitch BGA package For packages with SAC (tin-silver-copper) solder balls, use the following constant compressive loads: - 7g per solder ball for 0.5mm pitch MBGA package - 12g per solder ball for 0.8mm pitch UBGA package - 14g per solder ball for 0.92mm hex pitch FBGA package - 15g per solder ball for 1.00mm hex pitch FBGA package - 16g per solder ball for 1.00mm pitch FBGA package - 24g per solder ball for 1.27mm pitch BGA package For heat-sink application, Intel's recommendation is to not exceed 20g load per solder ball Your PCB and the supporting frame should be designed to withstand the pressure of the downward force to prevent bending or flexing of your PCB.Can a 9-transceiver channel Arria V GT device support an Rx only channel that already has four 6.144-Gbps duplex or Tx channels?
Description No, a 9-transceiver channel Arria® V GT device cannot support an Rx only channel that already has four 6.144-Gbps duplex or Tx channels. Due to a bug in the Quartus® II software versions 13.1 and earlier, the Fitter will not produce an error message for the configuration above. Resolution This problem is fixed in Quartus II software version 13.1 and an error message is produced with the above illegal configuration.Does the Advanced clock phase control adjustment in the HPS DDR3 work?
Description You may notice the Advanced clock phase control setting in the HPS GUI PHY Settings tab. Changing the phase value has no effect on the phase of the PLL output clocks. Resolution The Advanced clock phase control adjustment will be removed in a future version of the Quartus® II software. This problem was fixed in Quartus® II software version 13.1Is programming of a serial configuration device that is different from one selected in a .jic file possible?
Description The Quartus® II programmer supports programming of serial configuration devices via JTAG and the Serial Flash Loader which are a higher density than the device that the .jic file was originally targeted at. For example a .jic file that was targeted to an EPCS64 device may be used to program an EPCS128 device using the Quartus II programmer. SVF and JAM files that are generated from the .jic file may only be used to program the targeted device. The Quartus II programmer will allow an EPCQ256 device to be programmed by a .jic file targeted at a lower density device. In this case FPGA configuration may fail due to a difference in the format of the data for devices of 256Mb or greater. Resolution The Quartus II prgrammer is scheduled to be updated to not allow programming of EPCQ256 devices using .jic files intended for lower density devices.How do I change the clock frequency of the USB-Blaster II download cable?
Description The USB-Blaster™ II download cable has a default clock frequency for TCK (JTAG) or DCLK (Active Serial programming) of 24MHz. The frequency may be changed to lower frequencies where signal integrity and timing does not allow operation at 24MHz. Resolution The following comamnd may be used to change the clock frequency of the USB-Blaster II: jtagconfig --setparam <cable number> JtagClock <frequency> <cable number> is the USB-Blaster II cable to be modified. <frequency> is the desired TCK or DCLK frequency. 24M, 16M and 6M are supported. Related Articles What is the nominal operational frequency of TCK in the USB-Blaster download cable? Why does Quartus II Programmer prompt the error message Can't recognize silicon ID when programming an EPCS/EPCQ serial flash device with a .jic file using the USB-Blaster II download cable? Can I change the TCK frequency when using the ByteBlasterMV or ByteBlaster II download cables? Why does the TCK frequency setting of the USB-Blaster II download cable revert to the default value of 24 MHz after being changed? Can I change the TCK frequency when using the USB-Blaster download cable?The Text Editor toolbar is not displayed in the Quartus II software
Description The Text Editor toolbar is not displayed. Resolution To display the Text Editor toolbar, perform the following:1. Open the Text Editor,2. On the Window menu of the main Quartus II window, click Detach Window.3. Right-click anywhere on the menu bar of the Text Editor.4. Click Text Editor.Audio Embed IP Design Transmits Unstable 3G Video Image
Description Designs using SDI Audio Embed IP core transmit unstable and flickering 3G video images. This issue affects all designs using the SDI Audio Embed MegaCore function version 13.1. Resolution To work around this problem, set exclusive clock group to aud_clk and vid_clk of the audio_embed block. Add the following line to the audio_embed.sdc file. set_false_path -to [get keepers {*audio_embed_core:*|g_audio_pair*toggle_meta}]Why can I only see one source file for my Qsys component in the component editor?
Description When loading an existing custom peripheral into the Qsys component editor, only the top level HDL file is displayed in the GUI. On saving the peripheral, all other source files are lost from the generated _hw.tcl peripheral file. Resolution This is a current known issue in the Quartus® II 12.0 Qsys tool, and shall be fixed in a later version. The user will need to add the other required files into the component GUI before saving, or alternatively make edits to the peripheral using a text editor.The aclr related Recover/Removal timing path should be set false path when you enable the optional reset synchronization in the FIFO parameter editor
Description When you use the Quartus® II software v12.1sp1 FIFO parameter editor to generate a DCFIFO and enable the synchronous circuit to synchronize the aclr signal to rclk or wclk by checking the option "Add circuit to synchroniz the 'aclr' input to 'wrclk'/'rdclk'", you might see the recovery and removal timing path from aclr to synchronization registers which are supposed to be cut safely. Resolution Add the following sdc command in the sdc file to cut the related timing path manually: set_false_path -from [get_registers <aclr register name>] -to [get_registers <synchronization registers name>]