What is the maximum downward pressure that can be applied to the top of Intel® FPGA BGA packages?
Description The following guidelines refer to the downward pressure or compressive load that can be applied to the top of Intel® FPGA BGA packages: For packages with eutectic SnPb (tin-lead) balls, use the following constant compressive loads: - 3g per solder ball for 0.5mm pitch MBGA package - 6g per solder ball for 0.8mm pitch UBGA package - 7g per solder ball for 0.92mm hex pitch FBGA package - 8g per solder ball for 1.00mm hex pitch FBGA package - 8g per solder ball for 1.00mm pitch FBGA package - 12g per solder ball for 1.27mm pitch BGA package For packages with SAC (tin-silver-copper) solder balls, use the following constant compressive loads: - 7g per solder ball for 0.5mm pitch MBGA package - 12g per solder ball for 0.8mm pitch UBGA package - 14g per solder ball for 0.92mm hex pitch FBGA package - 15g per solder ball for 1.00mm hex pitch FBGA package - 16g per solder ball for 1.00mm pitch FBGA package - 24g per solder ball for 1.27mm pitch BGA package For heat-sink application, Intel's recommendation is to not exceed 20g load per solder ball Your PCB and the supporting frame should be designed to withstand the pressure of the downward force to prevent bending or flexing of your PCB.How do I change the clock frequency of the USB-Blaster II download cable?
Description The USB-Blaster™ II download cable has a default clock frequency for TCK (JTAG) or DCLK (Active Serial programming) of 24MHz. The frequency may be changed to lower frequencies where signal integrity and timing does not allow operation at 24MHz. Resolution The following comamnd may be used to change the clock frequency of the USB-Blaster II: jtagconfig --setparam <cable number> JtagClock <frequency> <cable number> is the USB-Blaster II cable to be modified. <frequency> is the desired TCK or DCLK frequency. 24M, 16M and 6M are supported. Related Articles What is the nominal operational frequency of TCK in the USB-Blaster download cable? Why does Quartus II Programmer prompt the error message Can't recognize silicon ID when programming an EPCS/EPCQ serial flash device with a .jic file using the USB-Blaster II download cable? Can I change the TCK frequency when using the ByteBlasterMV or ByteBlaster II download cables? Why does the TCK frequency setting of the USB-Blaster II download cable revert to the default value of 24 MHz after being changed? Can I change the TCK frequency when using the USB-Blaster download cable?Why are tREFI values in simulation and board measurement different from what is set in Altmemphy and UniPHY-based DDR2 SDRAM memory controller?
Description tREFI result in simulation and on the board might be larger than expected if you set tREFI to less than 7.8us in DDR/DDR2/LPDDR2 MegaWizard. DDR/DDR2/LPDDR2 SDRAM IP has a MEM_TREFI parameter, which defines the tREFI parameter in terms of memory clock cycles. Since the minimum value of this parameter is limited to 780, tREFI becomes larger when the memory clock is slower. For example, tREFI for DDR2 SDRAM should be 3.9us at >85C. But if the DDR2 memory clock is 125MHz(8ns), the minimum tREFI value can be 8ns x 780 = 6.24us. tREFI for DDR should be 7.8us. But if the DDR memory clock is 76.9MHz (13ns), the minimum tREFI value can be 13ns x 780 = 10.14us. Resolution As a workaround, if the DDR memory clock is below 100MHz or if you set tREFI to <7.8us on DDR2 memory, you can change the MEM_TREFI parameter in *ddrx_controller_wrapper (Altmemphy-based IP) file or *_c0 (UniPHY-based IP) file to correct the tREFI value. This problem has been fixed in Quartus® II Software Version 12.0.Can a 9-transceiver channel Arria V GT device support an Rx only channel that already has four 6.144-Gbps duplex or Tx channels?
Description No, a 9-transceiver channel Arria® V GT device cannot support an Rx only channel that already has four 6.144-Gbps duplex or Tx channels. Due to a bug in the Quartus® II software versions 13.1 and earlier, the Fitter will not produce an error message for the configuration above. Resolution This problem is fixed in Quartus II software version 13.1 and an error message is produced with the above illegal configuration.Synopsis VCS fails with an error Error- [MPD] Module previously declared
Description If you use the MegaWizard Plug-In Manager to create two or more IP variations in your design, simulation of the design with Synopsys VCS / VCS MX fails with an error similar to the following: Error-[MPD] Module previously declared The file set for simulating your entire design contains duplicate files. This duplication may occur if your design has multiple variations of the same IP core, or if different IP cores share some simulation files (for example, SystemVerilog packages common to multiple IP cores).For some IP cores, during IP file generation of an IP variation, a complete simulation file set is added to the <variation>_sim directory. Each variation's file set includes copies of all the IP simulation model files required to simulate the variation, including some files that may be shared with other IP cores.The concatenated list of all simulation files names for all IP variations (including the duplicate filenames) that is added to the VCS command line causes the error.NOTE: The file set does not include copies of the simulation library files that are installed in the quartus/eda/sim_lib directory and directories below it. Resolution Refer to the solution available http://www.altera.com/support/kdb/solutions/rd05172011_198.htmlWhy is my USB Blaster II not detected by Quartus II on Windows?
Description The USB-Blaster™ II may not be detected if there is a conflict between the USB-Blaster II driver and other 3rd party drivers on your PC. If your USB-Blaster II is not detected when running jtagconfig from the command line, you should inspect the Windows Device Manager. If there is a conflict with a different USB driver: The Altera® USB-Blaster II (Unconfigured) device is shown with a warning symbol in the Windows Device Manager The device status pane of the properties window for the Altera USB-Blaster II (Unconfigured) device displays (Code 38). Resolution To resolve this problem, the USB device that is in conflict with the USB-Blaster II should be unplugged. Many computers also use USB to communicate with built-in peripherals such as SD card readers. These devices may be disabled using the Windows Device Manager. This problem is scheduled to be resolved in a future release of the Quartus® II software.Error (10170): Verilog HDL syntax error at <Verilog_file>.v(line_number) near text ","; expecting an operand
Description Due to a problem in the Quartus® II software version 13.1 and later, you may get the following error when compiling a Verilog HDL file that has converted from a Block Design File (.bdf). The cause of the error is due to the generated Verilog HDL file has a extra comma in the port connections. Resolution To workaround the error, manually delete the extra comma in the <Verilog_file>.v(line_number). This problem is schedule to be fixed in future release of the Quartus II software.Vulnerability in JTAG server potentially allows a local attacker to execute arbitary code
Description With Intel® Quartus® Prime software versions from 15.1 to 18.0 and Quartus II software versions from 11.0 to 15.0, unquoted service paths may cause JTAG server to be vulnerable to the replacement of required executables. On reboot, these may be run with elevated privileges. This problem only occurs if the installation path contains spaces, if there are no spaces in the installation path then you are not affected by this vulnerability. This problem affects Intel Quartus Prime Pro, Standard and Lite editions as well as the subscription and web editions of the Quartus II software. This problem only affects installations on Windows. This problem also affects the Intel Quartus Prime and Quartus II standalone programmer version 18.0 and earlier. The Quartus II software and standalone programmer, version 10.1 and earlier, are not affected by this problem. Resolution To avoid this vulnerability, perform one of the following actions: If the Intel® Quartus® Prime software has already been installed to a path with spaces, remedy this vulnerability by downloading and installing the patch intel_sa00151_patch.exe (md5sum: 35ce4d672cef67efebdd3d5b866e58f3), then running the script that is extracted from the patch. If the Intel® Quartus® Prime software version 18.0 and earlier has not yet been installed, ensure that the installation path does not contain spaces. Install the Intel® Quartus® Prime software version 18.0 Update 1 or later where the vulnerability has been fixed. Acknowledgements: Intel® would like to thank Stefan (@Skanthak) for reporting this problem and working with us on coordinated disclosure.Why am I not able to assign a 3.3 V input to a bank with VCCIO connected to 2.5 V
Description The 3.3-V LVTTL and 3.3-V LVCMOS standards support VCCIO connected to 3.3 V, 3.0 V, or 2.5 V for input operation on Arria® V and Stratix® V device families. In versions 11.0 and 11.1 of the Quartus® II software, assigning a pin with a standard that requires VCCIO to be connected to 2.5 V (such as 2.5 V output) and a 3.3-V LVCMOS/LVTTL input will lead to a fitter error. Resolution Make an I/O standard assignment of 2.5 V to inputs that require the 3.3-V LVCMOS/LVTTL standards. The 2.5 V standard input specifications are the same as the 3.3-V specifcations except that Vil is 0.7 V rather than 0.8 V. See the following device datasheets for more information on input voltage thresholds: DC and Switching Characteristics for Stratix V Devices (PDF) Device Datasheet for Arria V Devices (PDF) This problem will be fixed in a future version of the Quartus II software. Related Articles Error (175001) : Could not place pin <pin name>How do I interpret the Logic Utilization number reported in the Quartus II Fitter report?
Description Logic utilization reported by the Quartus® II software is an estimation of how full the device is. It is given as a percentage, calculated from the number of half-adaptive logic modules (half-ALMs) available in the device, and the number of half-ALMs used in your design. In the Fitter report, the terms Combinational ALUT/register pairs and Combinational ALUT/register/register triples are used to indicate half-ALMs. Each ALM in Stratix® IV, Arria® II, Cyclone® IV or earlier families has 2 combinational logic LUTs and 2 registers, and they are paired off as combinational ALUT/register pairs. In Stratix V, Arria V and Cyclone V devices, there are two combinational LUTs and 4 registers per ALM, and they are grouped as combinational ALUT/register/register triples. Logic utilization is calculated by estimating how many half-ALMs are needed to fit a design, and expressing it as a percentage of the total number of half-ALMs available in the FPGA. Logic utilization is a good representation of how full a device is, rather than the register utilization percentage or the combinational logic utilization percentatge because it considers the aspects described below. The logic utilization metric is calculated as ( A - B C ) / (Total number of half-ALMs in the device) where A, B, and C are defined as follows: A: Combinational ALUT/register pairs used in final Placement or Combinational ALUT/register/register triples used in final Placement This is the actual number of completely or partially used half-ALMs in the design after placement B: Estimated pairs recoverable by pairing ALUTs and registers as design grows or Estimated triples recoverable by pairing ALUTs and registers as design grows This is the Fitter's estimate of how many half-ALMs could be freed up by taking half-ALMs that only use the combinational ALUT part, and half-ALMs that only use the registers, and grouping them up so that each half-ALM uses both the Combinational ALUT and register resources. For each possible grouping, a half-ALM is recovered. Therefore, this quantity is shown as a negative number in the report. Using this quantity helps to estimate how much logic would be needed if the Fitter could pack all logic as densely as possible. Note that this type of packing may not give the optimal result for routability and timing performance. C: Estimated Combinational ALUT/register pairs unavailable or Estimated Combinational ALUT/register/register tripes unavailable Due to a variety if reasons, the Fitter can not perfectly pack all the logic into every device resource. For example some half-ALMs cannot be paired up with other half-ALMs due to the number of inputs used, and some LABs cannot be fully packed with 10 ALMs due to routing restrictions. This quantity is the best estimate of the physical resources that will become unavailable for use, in terms of half-ALMs. Related Articles How do I interpret the terms Estimated pairs recoverable by pairing ALUTs and registers as design grows or Estimated triples recoverable by pairing ALUTs and registers as design grows in the Quartus II Fitter report?