Welcome to the Altera Community!

As the industry accelerates its transition from DDR4 to DDR5 and LPDDR5, memory choices are becoming a defining factor in system longevity, performance, and supply continuity. Altera is uniquely positioned to help customers navigate this shift with production-ready DDR5 and LPDDR5 solutions available today across a broad FPGA portfolio. DDR5 Is the New Standard Major memory vendors have announced plans for DDR4 end-of-life plans or significant production reductions, with full transitions to DDR5, LPDDR5, and next-generation memory already underway. While DDR4 will remain available for long lifecycle segments through multiple suppliers, new design starts today are increasingly looking to DDR5 and LPDDR5. Altera’s Head Start in DDR5 and LPDDR5 While DDR5 and LPDDR5 support is emerging across the industry, Altera stands apart with the broadest set of production devices supporting these standards across high-performance, mid-range, and power-optimized platforms: Agilex™ 7 M-Series and Agilex™ 5 devices support DDR5 and LPDDR5 for high-performance and embedded applications Altera is also planning to add LPDDR5 support within Agilex™ 3 devices, reinforcing its long-term design scalability. Competitive Advantage Across Every Market Tier Altera’s memory leadership spans across a range of design requirements: - High-Performance designs: Agilex™ 7 AGM032 and AGM039 support: DDR5 up to 5,600 MT/s LPDDR5 up to 5,500 MT/s - Mid-Range designs: Agilex™ 5 D-Series support: DDR5 up to 5,600 MT/s LPDDR5 up to 5,500 MT/s - Power/Cost-optimized designs: Agilex™ 3 support: LPDDR5 up to 2133 MT/s Unlike FPGA-only devices, Agilex integrates an optional HPS that allows DDR5 and LPDDR5 to function as a shared memory resource for both processing and acceleration, delivering higher effective bandwidth and system efficiency. Key Takeaway With DDR5 and LPDDR5 moving from ‘next-generation’ to ‘now,’ Altera offers customers a clear advantage: production-ready memory leadership, a broad and scalable FPGA portfolio, and a smooth transition path from DDR4 to DDR5—without waiting for future silicon. Download the The Agilex™ 5 SoC Memory Advantage with DDR5 and LPDDR5 White Paper

Using FPGAs and MCUs Collaboratively FPGAs and microcontrollers can be used alternatively in some applications, but they can also be used cooperatively.  FPGAs provide ultimate flexibility, but microcontrollers often include peripherals like USB or wireless interfaces that may be more convenient for communications and updates.  Both devices require supporting circuitry such as power, reference clocks, and storage.  Fortunately, these can often be shared when using FPGAs and microcontrollers together. This blog introduces an open-source tool that enables microcontrollers to load a programming file into a programmable device, and the practical application of this with the Raspberry Pi RP2350 MCU.  An Open Standard for Loading Programmable Devices Loading programmable devices from embedded processors is a common task.  The Jam Standard Test and Programming Language (STAPL) was originally developed by Altera engineers to address challenges in programming programmable logic devices (PLDs) in-system, such as proprietary file formats, vendor-specific algorithms, large file sizes, and long programming times. It provides a software-level standard for in-system programming (ISP), enabling flexibility and platform independence. Figure 1. In-system programming using the Jam File & Jam Player via an embedded processor.  In August 1999, JAM/STAPL was adopted as JEDEC standard JESD-71, making it an industry-recognized solution for JTAG-based programming. The language introduced features like compact file formats, branching, and looping, which reduced programming time and file size—ideal for embedded systems. JAM/STAPL consists of two main components:  Jam Composer: Generates Jam Files (.jam) containing programming algorithms and user data.  Jam Player: Interprets these files and applies JTAG vectors for programming and testing devices.  Over time, JAM/STAPL gained widespread support from PLD vendors, programming equipment makers, and test equipment manufacturers, becoming a cornerstone for in-field upgrades, prototyping, and production programming. Its evolution also included a byte-code format (.jbc) for even smaller files, making it suitable for resource-constrained embedded processors. Recently, Altera updated the license terms of the JAM and JBC players source code to MIT-0, to better clarify the usage rights.  A Practical Example The CycloMod board is an example of an FPGA and microcontroller working cooperatively.  The board combines a Raspberry Pi RP2350 MCU with a Cyclone® 10 LP FPGA in the SparkFun MicroMod form factor.  In this board, the FPGA is connected to some of the edge connector I/O, while the RP2350 is used to provide a flexible USB interface. The boot ROM in the RP2350 is leveraged extensively for firmware and FPGA image updates. Figure 2. CycloMod Board At 22mm x 22mm (including the card-edge connector), the MicroMod form factor is quite compact. This necessitates sharing resources, as there is not much room for multiple oscillators or flash devices.  The 12 MHz crystal oscillator in the RP2350 is easily shared by routing it to one of the GPIO clock outputs.  Both the Cyclone 10 LP device and RP2350 rely on external storage, but this can also be shared.  On this board, the flash is connected to the RP2350 to take advantage of the UF2 loading provided in the boot ROM, and the RP2350 loads the Cyclone FPGA.  The Cyclone 10 LP device supports active configuration with an external SPI flash device, but it can also be configured/programmed passively through JTAG. Figure 3. CycloMod Block Diagram  The STAPL byte code format (sometimes referred to as JBC) is compact enough to be used with microcontrollers like the RP2350.  Altera provides source code for implementing the “players” to process these files in embedded systems.  They offer players for the ASCII (JAM) and bytecode (JBC) versions of the files.   Altera’s Quartus® software provides the option to generate JAM and JBC files.  Since STAPL is a JEDEC standard, other FPGA vendors also support generating these files. Using the open-source code provided by Altera, the RP2350 is able to read a JBC file from flash and load the Cyclone 10 LP FPGA through the JTAG interface.  A Python script is provided to convert the JBC files to the UF2 format, which the RP2350 uses for drag-n-drop programming.  The script also adds a header with the file length and other details.  Thanks to the ingenuity of the UF2 format created by Microsoft, this enables cross platform field updates with zero software to install.  Results and Link to Source Porting Altera’s JBC player to the RP2350 eliminated the need for a second flash device and enabled user-friendly drag-n-drop FPGA updates.  The port is available on GitHub if you want to use this in your system.  https://github.com/steieio/pico-jbc  

We’re gearing up for AOC 2025! From December 9–11, we’ll be at the Gaylord National Resort & Convention Center in National Harbor, Maryland for AOC2025—one of North America’s premier events dedicated to electronic warfare and radar. Visit us at booth #505 to discover the latest innovations in our Agilex™ 9 Direct RF and Agilex™ 5 product families. What to Expect at Altera’s Booth #505:  1. Wideband and Agility Demo using Agilex 9: Overview: Discover the power of frequency hopping with Altera’s Direct RF FPGA, enhancing system resilience and adaptability. Key Features: Demonstrates swift frequency changes and wideband monitoring.  2. Wideband Channelizer Demo using Agilex 9: Overview: Wideband Channelizer features polyphase filter and 65 phases FFT blocks with variable channel support. Key Features: Demonstrates sampling rate that supports 64 GSPS with 32GHz instantaneous bandwidth. 3. Direction of Arrival Demo using Agilex 5: Overview: Explore Direction of Arriaval estimation and signal detection using AI-based approach with deployment of neural networks. Key Features: Demonstrates neural networks implementation using DSP Builder Advanced Blockset (DSPBA), showcasing end-to-end operation running real time inference. 4. Altera COTS Partner Showcase:    Come see our Agilex based COTS boards from partners including Annapolis Microsystems, CAES, Hitek, iWave Global, Mercury Systems, & Spectrum Controls.   We are hosting customer meetings at the event, contact your local Altera    salesperson to schedule a slot.