Internal Error: Sub-system: QHD, File: /quartus/comp/qhd/qhd_database_model_utils.cpp
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1.1 and earlier, you may see this error when running the import compile on an OpenCL™ BSP targetting an Intel® Stratix® 10 device. Resolution To work around this problem, please install patch 1.04 using Intel® Quartus® Prime Pro Edition Software version 18.1.1 as the baseline. patch 1.04 for Linux, patch 1.04 for windows, patch 1.04 readme file This problem is fixed in version 19.1 of the Intel® Quartus® Prime Pro Edition Software.Why does Linux fail to boot on my Intel® Stratix® 10 SoC when I use the f2s_free_clock as the HPS reference clock?
Description Due to a problem in Linux-socfpga Kernel version 4.17 for Intel® Stratix® 10 SoC from https://github.com/altera-opensource/linux-socfpga, the Linux Kernel may fail to boot if the HPS reference clock has been specified as the f2s_free_clk in the Hard Processor System Intel® Stratix® 10 FPGA IP in the Intel Quartus® Prime Pro Platform Designer. Resolution A patch for the linux-socfpga 4.18 Kernel is available to resolve this issue. Download and apply the patch below to the socfpga-4.18 branch of your local git clone of https://github.com/altera-opensource/linux-socfpga, then rebuild your Linux Kernel. 0001-fix-f2s_free_clk-setting_1.patch The patch for this issue has been released to https://github.com/altera-opensource/linux-socfpga.Why does Intel® Stratix® 10 HPS UART / I2C / SPI peripheral run at the wrong speed or not work in Linux?
Description Due to two different problems, UART, I2C, and SPI IP on Intel® Stratix® 10 SoC FPGA Hard Processor System (HPS) devices may run at the wrong speed on older Kernel Versions. SoC FPGA Linux Kernels 4.17 and later (post-June 2018) when a non-default MPU clock frequency is used: Fixed and patch uploaded to https://github.com/altera-opensource/linux-socfpga commit 23d4f7b2c6000e095399a6266ef35c213f93649e In SoC FPGA Linux 4.17 Kernels and later, the Stratix 10 Clock Manager driver extracts the clocking information from the FPGA bitstream. Only the reference clock frequencies are specified in the device tree. Due to a problem, some frequencies may be incorrect if the MPU frequency is set to a non-default value. SoC FPGA Linux Kernels 4.17 pre-June 2018, and 4.16 and earlier: The Linux Device Tree contains information on the clocking structure of the Intel® Stratix® 10 SoC FPGA Hard Processor System (HPS). It must reflect the clock setup in the Hard Processor System Intel Stratix 10 FPGA IP in the Intel® Quartus® Prime Pro Platform Designer system. If the clocking structure is not updated to reflect your board and design, peripherals may operate incorrectly in Linux. Typical problems are UART or I2C interfaces working in u-boot but which do not work in Linux. Due to a problem, some frequencies may be incorrect if the MPU frequency is set to a non-default value (workaround below) This issue has been fixed for newer Kernel versions. The clock information is read from the FPGA configuration bitstream and by an updated clock driver. Resolution SoC FPGA Linux Kernels 4.17 and later (post-June 2018) when a non-default MPU clock frequency is used This problem is fixed for the 4.18 kernel on https://github.com/altera-opensource/linux-socfpga with commit 23d4f7b2c6000e095399a6266ef35c213f93649e A patch is also available to work around this issue 0002_clk-pll-s10_L3L4clockFrequencyFix_1.patch Also, see related KDB: Why does Linux fail to boot on my Intel® Stratix® 10 SoC when I use the f2s_free_clock as the HPS reference clock? Soc FPGA Linux Kernels 4.17 pre June 2018 and 4.16 and earlier : See How do I update the Linux Device Tree for Stratix 10 SX to match the Clock settings in Platform Designer? for information on how to update the Linux Device Tree to reflect the clocking settings in your design. To work around the math error if non default MPU clock frequency is used - Manually set L3,L4 L4 Slow clock frequencies in the device tree ○ Leave the logic to describe the PLL's ○ Override the clocks from the L3 divider l3_main_free_clk: l3_main_free_clk { #clock-cells = <0>; #compatible = "altr,socfpga-s10-perip-clk"; #clocks = <&noc_free_clk>; #fixed-divider = <1>; clock-frequency = <400000000>; compatible = "fixed-clock" }; l4_sys_free_clk: l4_sys_free_clk { #clock-cells = <0>; #compatible = "altr,socfpga-s10-perip-clk"; #clocks = <&noc_free_clk>; #fixed-divider = <4>; clock-frequency = <100000000>; compatible = "fixed-clock" }; l4_main_clk: l4_main_clk { #clock-cells = <0>; #compatible = "altr,socfpga-s10-gate-clk"; #clocks = <&noc_clk>; clock-frequency = <400000000>; compatible = "fixed-clock"; #div-reg = <0x70 0 2>; #clk-gate = <0x30 1>; }; l4_mp_clk: l4_mp_clk { #clock-cells = <0>; #compatible = "altr,socfpga-s10-gate-clk"; #clocks = <&noc_clk>; clock-frequency = <200000000>; compatible = "fixed-clock"; #div-reg= <0x70 8 2>; #clk-gate = <0x30 2>; }; l4_sp_clk: l4_sp_clk { #clock-cells = <0>; #compatible = "altr,socfpga-s10-gate-clk"; #clocks = <&noc_clk>; clock-frequency = <100000000>; compatible = "fixed-clock"; #div-reg= <0x70 16 2>; #clk-gate = <0x30 3>; };Why does FPGA fabric (phase 2) configuration fail on my HPS Boot First Intel® Stratix® 10 SoC design?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1, phase 2 configuration of the FPGA fabric from the HPS as part of a HPS boot first flow on Intel Stratix® 10 SoC devices might fail when run from u-boot or Linux for large .RBF files. Resolution Patch 0.19 for the Intel® Quartus® Prime Pro Edition Software version 18.1 is available to fix this problem. Download and install the patch from the following links, recompile your Intel Quartus Prime Pro Edition Software project and recreate the programming file: Patch 0.19 for Quartus Prime Pro version 18.1 for Linux (.run) Patch 0.19 for Quartus Prime Pro version 18.1 for Windows (.exe) Readme for Patch 0.19 for Quartus Prime Pro version 18.1 (.txt) This has been fixed in the Intel Quartus Prime Pro Edition Software v18.1.1Why does Intel® Quartus® Prime Pro Edition Software version 17.1 assembler fail to generate the Partial Reconfiguration programming files?
Description Due to bitstream configuration issues, Partial Reconfiguration bitstream generation was disabled by default in the Intel® Quartus® Prime Pro Edition Software version 17.1. You might see the following warning message during the Assembler stage while running the Partial Reconfiguration compilation flow: Critical Warning (19088): Compilation Report contains advance information. Specifications for device <Stratix®10> are subject to change. Contact Intel for information on availability. No partial reconfiguration programming files will be generated. Resolution To fix this issue, install the following patch on top of the Intel® Quartus® Prime Pro Edition Software version 17.1: quartus-17.1-0.01-windows.exe quartus-17.1-0.01-linux.run quartus-17.1-0.01-readme.txt This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 17.1.1.How do I use the Avery BFM to simulate PCI Express Gen3x16 designs using Quartus Prime Pro Edition Software 17.1 Stratix 10 ES Editions?
Description Stratix® 10 devices support PCI® Express Hard IP modes up to Gen3x16. Simulating Gen3x16 requires using a third-party root complex BFM. This document describes how to set up a simulation using a third-party BFM. The set up focuses on an Avery BFM and is targeted for the Mentor ModelSim and Synopsys VCS simulators. You can adapt these steps to other third-party BFMs and other simulation software. Third-party BFMs are only supported for Gen3x16 simulation. For modes up to Gen3x8, follow the instructions in the Stratix 10 Avalon-ST Interface for PCIe Solutions User Guide. Note: The Intel FPGA root complex bus functional model (BFM) only supports modes up to Gen3x8. Resolution Follow the steps in this document for a walkthrough on setting up a Gen3x16 simulation using the Avery BFM. The simulation scripts required for the walkthrough can be found here.Error (170012): Fitter requires "XXX" LABs to implement the design, but the device contains only "XXX" LABs
Description Due to a problem in the Intel® Quartus® Prime Pro edition software version 19.4, you may see the above error when using VQM netlist as source for the compilation in Intel® Stratix® 10 Devices. The Intel Quartus Prime Pro edition software version 19.4 does not support "WYSIWYG primitives " resynthesis. If a VQM File contains WYSIWYG primitives, the Intel Quartus Prime Compiler creates atom representations from those WYSIWYG primitives as it synthesizes the design, so that the atoms preserve the WYSIWYG structure of the netlist file. Resolution A patch is avaliable to fix this problem for the Intel® Quartus® Prime Pro Edition software version 19.4. Download and install Patch 0.05 from the appropriate link below Download the version 19.4 Patch 0.05 for Windows(.exe). Download the version 19.4 Patch 0.05 for Linux (.run). Download the Readme for Patch 0.05 (.txt). This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.Why does my OS freeze when using the Intel® Stratix® 10 PCIe Hard IP core?
Description Due to a problem with the Intel® Quartus® Prime Pro Edition Software version 17.1, you may see your operating system freeze on boot or experience no PCIe* linkup, when using the Stratix® 10 GX PCIe Hard IP core. This is due to an improper setting in the Intel® Quartus® software. This issue affects Stratix® 10 GX devices with ES1 L-Tiles, ES2 L-Tiles, or ES H-Tiles. Resolution Using the links below, install patch 0.02 on top of Quartus Prime Pro 17.1. Regenerate the Intel® Stratix® 10 PCIe Hard IP variant and recompile your design. Readme Linux patch Windows patch This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 17.1.1.Why does my JIC programming operation fails at the 'Verify' step with the Quartus® Prime Pro Edition Software Programmer version 18.1
Description Due to a problem with the 'fast write' operations performed by the Quartus® Prime Pro Edition Programmer to a flash device, you may experience data corruption after a programming operation, or you may see an error in the 'Verify' step if it has been enabled. Resolution To work around this problem, download and install the patch file below. The patch disables the 'fast write' operations for the Quartus® Prime Pro Edition software Programmer version 18.1, forcing the software to use the 'normal write' operation. A time increment is expected on programming operation to a flash device after the patch has been installed.Where can I download the schematics files for the FMC loopback daughter board designed for the Intel® Stratix® 10 SX SoC Development Kit?
Description The schematic and the layout files for the FPGA Mezzanine Card (FMC) loopback daughter board designed for the Intel® Stratix® 10 SX SoC Development Kit can be downloaded from the link below. Resolution FMC_loopback_schematics_and_layout.zip