Error: Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see this error message during the Support-Logic Generation stage when compiling a design on the Windows* Operating System. This error occurs when Windows* long path support is disabled. Windows* limits the combined length of a file name and its path to 260 characters. If the project path exceeds this limit, the Quartus® Software cannot access required IP or design files. Resolution To work around this problem, enable Windows* long path support by updating the registry: a) Open Registry Editor: Press Windows Key + R, type regedit, and press Enter. b) Navigate to HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem c) Find LongPathsEnabled. Double-click it and set "Value data" to 1. If the LongPathsEnabled doesn't exist, right-click, select New > DWORD (32-bit) Value, and name it LongPathsEnabled. d) Restart your computer. This error message will be enhanced in a future release of the Quartus ® Prime Pro Edition Software.Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_traversal_manager.cpp, Line: 2769
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 to 25.3.1, you might see this internal error at the Fitter Finalize stage when the design contains combinational loops. Static Timing Analysis analyzes timing graphs without loops. When a combinational loop is detected, Timing Analyzer replaces the loop with bypass edges whose delays represent the longest path through the loop. When new timing corners are added later in the finalize stage, the bypass edge delays may not be computed for all corners, causing an internal consistency check to fail and resulting in an internal error. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.Why does niosv-download return “Invalid reset option” when executing reset from debug module?
Description Due to a problem in the Ashling RiscFree IDE for Altera® software, the niosv-download returns “Invalid reset option” when executing reset from debug module for designs targeting Nios ® V processor. The affected versions are: Software version 25.2.1 (version dated 9 th May 2025, paired with Quartus® Prime Pro software version 25.1.1 and Quartus® Prime Standard software version 25.1) Software version 25.3.1 (version dated 1 st Aug 2025, paired with Quartus® Prime Pro software version 25.3.1) Software version 25.4.1 (version dated 31 st Oct 2025, paired with Quartus® Prime Pro software version 26.1) The problem is caused by Ashling GDBServer failing to execute software reset (swreset), and niosv-download is using Ashling GDBServer to communicate with the processor. Thus, this failure prompts the “Invalid reset option” message when executing “niosv-download –r". Resolution To work around this problem, use the argument “-o” to change from Ashling GDBserver to OpenOCD. $ niosv-download –r -o This problem is fixed beginning with the Ashling RiscFree IDE for Altera® Quartus® software version 26.1.1-C, which is paired with Quartus® Prime Pro software version 26.1.1. Related Articles NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10) | Altera Community - 352387Why do setup and minimum pulse width timing violations occur in the LVDS SERDES IP Design Example?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1 and earlier, you may encounter setup and minimum pulse width timing violations in the LVDS SERDES IP Design Example. This issue is caused by an incorrect value of the vco_data_rate_ratio parameter used in the LVDS SERDES IP, which leads to improper timing constraints and resulting violations. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Resolution To work around this issue, follow the steps below: Step 1: In the auto-generated file intel_lvds_core10_ph2_hw_ed_synth_intel_lvds_0_example_design_example_design_intel_lvds_core10_ph2_191_<string>.sv, Original: .vco_data_rate_ratio(0), Change to: .vco_data_rate_ratio(<correct_vco_data_rate_ratio>), Step 2: In the auto-generated file ed_synth_intel_lvds_0_example_design_example_design_intel_lvds_core10_ph2_191_<string>.sdc, add this SDC constraint set ip_params(vco_data_rate_ratio) <correct_vco_data_rate_ratio> Step 3: Re-compile the design The correct vco_data_rate_ratio parameter value based on the LVDS SERDES IP data rate (Mbps) shown in table below: Use the appropriate vco_data_rate_ratio based on the LVDS SERDES IP data rate: data_rate >= 600 Mbps 1 600 Mbps > data_rate >= 300 Mbps 2 data_rate < 300 Mbps 4 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Related IP Core: LVDS SERDES IPWhy does the Nios® V processor without data cache hang during a flash read operation using the Generic Serial Flash Interface (GSFI) IP HAL driver?
Description When performing a read operation on a flash device using the GSFI IP HAL driver, a Nios® V processor configured without a data cache may hang and stop functioning correctly due to an issue in the HAL driver. The HAL driver attempts to flush the data cache even when no data cache is present. This incorrect behavior places the processor into a non-deterministic state, which can cause the system to freeze. Resolution To work around this issue, update the following line in the intel_gsfi_read() function. Original: alt_dcache_flush_no_writeback((alt_u8*)qspi_flash_info->data_base + offset, length); Change to: #if ALT_CPU_DCACHE_SIZE > 0 alt_dcache_flush_no_writeback((alt_u8*)qspi_flash_info->data_base + offset, length); #endif This modification ensures that the data cache flush operation is performed only when a data cache is present. This issue will be fixed in a future Quartus® Prime Software release.Why does the read/write HAL API fail when the access length reaches the last byte of flash memory when using the Generic Serial Flash Interface (GSFI) IP HAL driver?
Description When performing a read or write operation on a flash memory device using the GSFI IP HAL read/write API, the API may incorrectly return an EINVAL error code. This issue occurs because the operation end address is miscalculated. As a result, the GSFI IP HAL API incorrectly determines that the operation end address exceeds the valid flash memory range and flags the access length as invalid. For example, when reading or writing the entire 1 GiB flash device, the operation reaches the last byte with an access length of 2147483648 bytes. In this case, the GSFI IP HAL API miscalculates the operation end address as 0x80000000, which exceeds the flash end address of 0x7FFFFFFF. Consequently, the access length is incorrectly treated as invalid, and a false EINVAL error code is returned. This issue does not occur when reading from or writing to other addresses that do not include the last byte of the flash memory. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Resolution To work around this issue, update the following line in the intel_gsfi_validate_read_write_arguments() Original: end_address = start_address + length; Change to: end_address = start_address + length - 1; This correction ensures the calculated end address does not exceed the valid flash memory range. This issue will be fixed in a future Quartus® Prime Design Software release.Why does an SDI hardware failure occur in single‑rate HD‑SDI parallel loopback without an external VCXO at 1280×720p24 across all FPGA device families?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1 and earlier, an SDI hardware failure may be observed when using the Single‑Rate HD‑SDI Parallel Loopback design without an external VCXO and selecting the 1280 × 720p24 video standard on all SDI‑supported FPGA device families. This issue does not affect multi‑rate or triple‑rate HD modes. Resolution This issue is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. For users who must remain on Quartus® version 26.1 or earlier, use the following workaround: Regenerate the design using Quartus® Prime Pro Edition Software version 26.1.1 or later. In your target project, replace the entire pfd folder with the corresponding folder from the newly generated design. The updated PFD module can be found at: <Your_Design_Folder>/rtl/loopback/pfdWhy does the Tensor FIR IP generation fail with a missing-file error?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, you might see an error related to a missing file when performing Tensor FIR FPGA IP generation. Example error output Info: tensor: "Generating: tensor_tensor_fir_100_vs35orq" Error: add_fileset_file: No such file <user directory>/26.1/quartus/dspba/backend/include/cmd_tools/share/bp2_prog_c.h while executing "add_fileset_file "bp2_prog_c.h" OTHER PATH "$bepath/include/cmd_tools/share/bp2_prog_c.h"" (procedure "gen_files" line 327) invoked from within "gen_files $entity "VHDL"" (procedure "gen_sim_vhdl_files" line 2) invoked from within "gen_sim_vhdl_files tensor_tensor_fir_100_vs35orq" Info: tensor: Done "tensor" with 2 modules, 25 files Info: Finished: Create simulation model Error: SPD file was not generated: <user directory>/tensor/tensor.spd Error: Could not generate simulation scripts There are three operation modes for the Tensor FIR IP: Memory-Mapped non-Memory-Mapped Auto-Programming The missing -file error occurs when using modes 1 and 2. Mode 3 is not affected by the error. Resolution A patch is available to fix this problem in Quartus Prime Pro Edition Software version 26.1. Download and install patch 0.01dsp below. The error will be fixed in future versions of the Quartus Prime Pro Edition Software.Why does Nios® V/g processor experiences data corruption when it is enabled with TCM and ECC?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 26.1, data corruption might occur in Nios ® V/g processor designs with tightly coupled memory (TCM) and error correction code (ECC). Both features must be enabled to observe this problem. It is caused by an RTL bug in the processor, which renders failure when the processor executes sw (store word), followed by sh (store halfword) or sb (store byte) instructions. For example, # Initially, value of Y is 0x0001CCCC. li t0, 0x12345678 li t1, 0x200A sw t0, 0(Z) # Store 0x12345678 word into Z sh t1, 0(Y) # Store 0x200A into lower half of Y Result Final value of Y Description Expected 0x0001200A Upper-half of Y is preserved as 0x0001, while lower-half of Y is changed to 0x200A. Actual (Data Corruption) 0x1234200A Upper-half of Y is corrupted to 0x1234, while lower-half of Y is changed to 0x200A. The 0x1234 is from the previous Store Word (sw) instruction. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 26.1, apply either one of the solutions below: Disable TCM. Disable ECC. This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software.
What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.2?
Description The latest device firmware for Quartus® Prime Pro Edition Software version 24.2 is available for download below. Fixes for the following problems are included in the latest release (The newest release contains all prior fixes and supersedes earlier device firmware releases). Change Log Firmware version 0.04fw: This patch fixes the issue of incorrect data retrieval in the GET_I2C_TELEMETRY command. Firmware version 0.10fw: This patch fixes to reissue PLL lock request to achieve true independent PERST. Firmware version 0.54fw: This patch fixes issue where the HPS will get stuck at FSBL on certain units above Quartus 22.2B94 / or with firmware above 22.4B94. Firmware version 0.59fw: This patch includes fix to improves voltage sensor reading stability. Please also see the following links: Updating the SDM Firmware in the Agilex® 7 FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution Download the latest device firmware below. Note: Patches must be applied to the Quartus® Prime Pro Edition Software and the Quartus® Prime Pro Edition Software Programmer and Tools. Recompilation is not required. All programming files should be recreated. Re-run programming file generation or conversion using the Quartus® Prime Software programming file generator.