How can I tell if a Raw Binary File (.rbf) is a PR Bitstream File?
Description A customer can tell if a Raw Binary File (.rbf) is a PR Bitstream File by following the information below. Resolution A PR Bitstream will start with the value 0x97566593 at offset 0x000 AND Have the value 0x5052(PR) at offset 0x00C.Why does Partial Reconfiguration (PR) via HPS fail only when using encrypted PR bitstreams?
Description Partial Reconfiguration (PR) via HPS fails only when using encrypted PR bitstreams. This failure only happened on encrypted PR bitstream and not base bitstream. Error message display: root@agilex:~# mv /tmp/pr.rbf /lib/firmware/persona0.rbf root@agilex:~# /usr/bin/dtbt -a /lib/firmware/agilex7_pr_fpga_static_region.dtbo Applying dtbo: /lib/firmware/agilex7_pr_fpga_static_region.dtbo [ 251.625026] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/ranges [ 251.638872] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/external-fpga-config [ 251.649792] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/clocks [ 251.659426] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/clock-names [ 251.669543] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clk_0 [ 251.679105] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/freeze_controller_0 [ 251.693803] of-fpga-region fpga-region:fpga_pr_region0: FPGA Region probed root@agilex:~# /usr/bin/dtbt -a /lib/firmware/agilex7_pr_persona0.dtbo Applying dtbo: /lib/firmware/agilex7_pr_persona0.dtbo [ 262.265981] fpga_manager fpga0: writing persona0.rbf to Stratix10 SOC FPGA Manager [ 267.497950] Stratix10 SoC FPGA manager firmware:svc:fpga-mgr: timeout waiting for svc layer buffers Resolution This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition software.Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.Error: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of space
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1, you might see this error when compiling your design in Design Space Explorer II. Error: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of space (Command was: lmap panel_name [::qed_lib::rdb_util::get_report_panel_names_matching -panel_name {} -string_match {Synthesis||Logic Synthesis Stage||Partition*||*Optimization Results||Multiplier Implementations||Multiplier Implementation Report} -regexp_match {}] {::qed_lib::rdb_util::get_report_panel_str -panel_name $panel_name})} Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.21 This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.
Why does my Stratix® 10 FPGA device fail to configure if there is a delay between power up and configuration?
Description Due to a problem in the Stratix® 10 FPGA devices listed below, if it takes longer than 18 seconds from the completion of power up to the configuration of the first 256 Kb of configuration bitstream your Stratix® 10 FPGA device may fail to configure. The root cause lies in the Boot ROM, which causes a watchdog timer to overflow and causes the device to hang. This issue applies to all configuration schemes. Configuration via Protocol (CvP) is not impacted if the programming of the periphery meets the 18 seconds requirement as described in the workaround. This issue does not apply to reconfiguration. If you are using the FPGA Download Cable II and you encounter this issue, you will see the following error message: Error (20068): Configuration error, you must power-cycle the device to recover from this condition. To avoid this error, you must ensure that the device is configured within 18 seconds after completion of the power-on sequence. This issue affects the following Stratix 10 FPGA devices: Impacted Stratix 10 GX FPGA variants Stratix 10 GX 1100 H-Tile ES1 Stratix 10 GX 2800 H-Tile ES2 Stratix 10 GX 2800 H-Tile ES3 Stratix 10 GX 2800 L-Tile ES3 Stratix 10 GX 2500 L-Tile Production Stratix 10 GX 2800 L-Tile Production Impacted Stratix 10 SX FPGA variants Stratix 10 SX 1100 H-Tile ES1 Stratix 10 SX 2800 L-Tile ES1 Stratix 10 SX 2800 L-Tile ES2 Stratix 10 SX 2800 L-Tile ES3 Stratix 10 SX 2800 H-Tile ES3 Impacted Stratix 10 MX FPGA variants Stratix 10 MX 2100 H-Tile ES1 Impacted Stratix 10 TX FPGA variants Stratix 10 TX 2800 ES1 Stratix 10 TX 2100 ES1 Resolution The recommended conditions for configuration are shown in Figure 4 of the Stratix® 10 Configuration User Guide. After successful configuration the nSTATUS pin is driven high within 110 ms of nCONFIG pin transitioning to high. The observed behavior with impacted devices shows that the nSTATUS pin remains low until the device is power cycled. There are both hardware and software workarounds possible for this issue, which are described in the errata document. The hardware and software workarounds are common to all impacted Stratix® 10 device variants. To implement the software workaround, you are required to download and install patch 0.13 along with Quartus® Prime Pro Edition version 18.0 from the below links. This problem is due to be fixed in the production version of the Stratix 10 SX 2800/2500 L-Tile FPGA device. If you are using an Stratix 10 GX 2800/2500 L-Tile FPGA device and a fix is required, move to the Stratix 10 SX 2800/2500 L-Tile FPGA device, which is drop-in compatible.Is the timing model for Stratix® 10 1SX040, 1ST040, and 1SG040 FPGA devices correct?
Description No, due to a problem in the Quartus® Prime Pro Edition Software v21.2 and earlier, the timing model for Stratix® 10 1SX040, 1ST040 and 1SG040 FPGA devices is not correct. This occurs because the timing model for vertical (C2/C3/C4/C16) routing wires are miscalculated. Errors range from few ps to 50 ps per path, with 150 ps in the worst corner for the worst wire. This problem only affects Stratix® 10 1SX040 (GX/SX H-Tile) / 1SG040 (TX E-Tile) FPGA devices. Resolution To work around this problem for projects using devices 1ST040xxxx (TX E-Tile), download and install the patch according to the versions of your Quartus® Prime Software. Patch 0.60 for Quartus Prime Pro Edition Software v20.1: Quartus® Prime Pro Edition Software v20.1 Solution Patch 0.60 for Windows (.exe) Quartus® Prime Pro Edition Software v20.1 Solution Patch 0.60 for Linux (.run) Readme for Quartus® Prime Pro Edition Software v20.1 Solution Patch 0.60 (.txt) Patch 0.57 for Intel Quartus Prime Pro Edition Software v20.2: Quartus® Prime Pro Edition Software v20.2 Solution Patch 0.57 for Windows (.exe) Quartus® Prime Pro Edition Software v20.2 Solution Patch 0.57 for Linux (.run) Readme for Quartus® Prime Pro Edition Software v20.2 Solution Patch 0.57 (.txt) Patch 0.74 for Intel Quartus Prime Pro Edition Software v20.3: Quartus® Prime Pro Edition Software v20.3 Solution Patch 0.74 for Windows (.exe) Quartus® Prime Pro Edition Software v20.3 Solution Patch 0.74 for Linux (.run) Readme for Quartus® Prime Pro Edition Software v20.3 Solution Patch 0.74 (.txt) Patch 0.43 for Intel Quartus Prime Pro Edition Software v20.4: Quartus® Prime Pro Edition Software v20.4 Solution Patch 0.43 for Windows (.exe) Quartus® Prime Pro Edition Software v20.4 Solution Patch 0.43 for Linux (.run) Readme for Quartus® Prime Pro Edition Software v20.4 Solution Patch 0.43 (.txt) To work around this problem for projects using devices 1ST040xxxx (TX E-Tile) or 1SX040xxx (GX/SX H-Tile), download and install the patch according to the versions of your Intel® Quartus® Prime Software. Patch 0.50 for Intel Quartus Prime Pro Edition Software v21.1: Quartus® Prime Pro Edition software version 21.1 Solution Patch 0.50 for Windows (.exe) Quartus® Prime Pro Edition software version 21.1 Solution Patch 0.50 for Linux (.run) Readme for Quartus® Prime Pro Edition software version 21.1 Solution Patch 0.50 (.txt) Patch 0.30 for Intel Quartus Prime Pro Edition Software v21.2: Quartus® Prime Pro Edition Software v21.2 Solution Patch 0.30 for Windows (.exe) Quartus® Prime Pro Edition Software v21.2 Solution Patch 0.30 for Linux (.run) Readme for Quartus® Prime Pro Edition Software v21.2 Solution Patch 0.30 (.txt) Once the patch is installed, perform the following actions: Save <design>.sta.rpt before running. Run quartus_sta –force_dat <project> in the command line. Recompile the design if there are any negative slacks. This problem only affects the timing model for the devices listed. The other Stratix® 10 FPGA devices are not affected. This problem is fixed beginning with version 21.3 of the Quartus® Prime Pro Edition Software.Is there a known problem with the per pin RLC value in IBIS files generated in Quartus® Prime Pro Edition Software for Stratix®10 MX FPGA devices?
Description Yes, due to a known problem with Quartus® Prime Pro Edition Software version 20.3 and earlier, when generating an IBIS file for Stratix® 10 MX 1650 and 2100 density FPGA devices in UF55 package with "Print per pin RLC package model with mutual coupling' option enabled, the R-value per pin in the generated .ibs file is incorrect. Resolution Download the attached file to obtain the correct per-pin RLC value for Stratix® 10 MX 1650 and 2100 density FPGA devices in the UF55 package.How can the generation of the iossm_bf_cpu_cpu.tr file be disabled when simulating the Stratix® 10 DDR4 IP?
Description Due to a problem in the Quartus® Prime Software versions 18.0 and 18.1, a large trace file called iossm_bf_cpu_cpu.tr is generated when you simulate a design containing the Stratix® 10 DDR4 IP. Resolution To disable the generation of the iossm_bf_cpu_cpu.tr file, download and install the Quartus® Prime Software version 18.1 patch 0.21. > Download the Readme (.txt) for the version 18.1 patch 0.21 > Download the version 18.1 patch 0.21 for Windows (.exe) > Download the version 18.1 patch 0.21 for Linux (.run)Why does my JIC programming operation fails at the 'Verify' step with the Quartus® Prime Pro Edition Software Programmer version 18.1
Description Due to a problem with the 'fast write' operations performed by the Quartus® Prime Pro Edition Programmer to a flash device, you may experience data corruption after a programming operation, or you may see an error in the 'Verify' step if it has been enabled. Resolution To work around this problem, download and install the patch file below. The patch disables the 'fast write' operations for the Quartus® Prime Pro Edition software Programmer version 18.1, forcing the software to use the 'normal write' operation. A time increment is expected on programming operation to a flash device after the patch has been installed.Error: ex_25g.alt_e25s10_0: The current selected device "1SX280HU2F50E2VGS1" is not supported by this IP, please select a valid device to generate the IP.
Description Due to a problem with the Quartus® Prime Pro Software version 18.1, you may see the above error in the IP Parameter Editor System Messages pane when trying to generate a 25G Ethernet Stratix® 10 FPGA IP instance for an Stratix® 10 device with H-Tile ES1 or ES2 silicon. Resolution To work around this problem, you must either target an Stratix® 10 FPGA device with H-Tile ES3 or Production silicon when creating your project in Quartus® Prime Pro software or you can install the patch below for Quartus® Prime Pro v18.1. This problem is scheduled to be fixed in a future release of the Quartus® Prime Software.
