Why do I unexpectedly observe intermittent DDM Errors?
Description Beginning January 10, 2026, executing commands in the terminal or GUI of Quartus® Prime Pro Edition software, Quartus Embedded Edition software or select standalone tools may cause the software or tool to crash with an error similar to the crash signature shown below. This error affects: Quartus Prime Pro Software versions v23.3 through v25.3.1 Standalone Quartus Prime Pro Programmer v23.3 through v25.3.1 Standalone Quartus Prime Pro Embedded Edition v25.3 and v25.3.1 Standalone Quartus Prime Pro Power Thermal Analyzer v25.3 through v25.3.1 This issue is not observed in Quartus Prime Pro Edition versions 23.2 or prior or Quartus Prime Standard Edition. Crash Signature: Error (22912): Unhandled exception: Fatal Error: Assertion failed tools/cpp/ddm/ddm_assessor.cpp:53: DDM_T::verify_token(token) : Cannot identify the client from function assertion_error in tools/cpp/ddm_report/ddm_report_msg.cpp@465 *** Fatal Error: Program termination requested *** *** Below is the stack trace at the time the error occurred. *** The lines beginning "Err Handler" represent frames relating *** to generating this report. *** The point at which the error occurred is somewhere after these lines. *** There may be a few frames representing standard/library code *** before the Quartus frames begin. *** The search for the error should begin with the Quartus frames. *** Unwinder: libunwind *** Stack depth: 15 Quartus 0x24e67: err_terminator() + 0x1bc (ccl_err) Quartus 0xb036a: __cxxabiv1::__terminate(void (*)()) + 0xa (stdc++) Quartus 0xb03d5: (stdc++) Quartus 0xb0628: (stdc++) Quartus 0x1680d: void ddm_throw<DDM_RUNTIME_ERROR>(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x26d (ddm_report) Quartus 0x13fae: DDM_REPORT::DDM_ASSERTION_HANDLER::assertion_error(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >) const + 0xde (ddm_report) Quartus 0x12a52: DDM_REPORT::ASSERTION_HANDLER::error(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >) + 0x72 (ddm_report) Quartus 0x13e64: DDM_REPORT::detail::assert_at_line(char const*, char const*, int, char const*, ...) + 0x1b4 (ddm_report) Quartus 0x205fb0: ddm_set_lassessor(DDM_T_ASSESSOR*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x60 (ddm) Quartus 0xf4445: DMS_MANAGER::DMS_MANAGER() + 0x5c5 (dni_dms) Quartus 0xf45b2: DMS_MANAGER::get() + 0x7a (dni_dms) Quartus 0xf6db4: _GLOBAL__sub_I_dms_manager.cpp + 0x58 (dni_dms) Quartus 0x647e: (ld-linux-x86-64) Quartus 0x6568: (ld-linux-x86-64) Quartus 0x202ca: (ld-linux-x86-64) Resolution To work around this problem: For Windows machines Download and unzip the Quartus Prime Pro version zip file that matches your Quartus Prime Pro version from this KDB. Double click on the executable ending in “windows.exe”. When the GUI pops up, press Next. Note that the GUI may look slightly different depending on the version of Quartus you are using. Accept the license agreement Specify the directory where the patch needs to be applied which may be a different location than Quartus install if you have standalone tools in a different directory from your Quartus Prime Pro software installation. Keep “Allow Patch to be uninstalled” selected. Select the software in which to install the patch: The patch will install in the directory of the software or tool you have selected. You will see an uninstall directory for the patch in your software or tool folder where patch is installed; it will contain an executable to uninstall the patch if required for any reason. To confirm patch is installed, you can run quartus_sh -v or corresponding version command for your tool via command line. Alternatively, you can Open Quartus in the GUI and select Help → About Quartus Prime in the main menu. If you are opening up a standalone tool you will navigate to Help-> About <tool_name>. For the Command Line Implementation of the patch in Windows, use the following command: <patch_filename.exe> --mode unattended --installdir <your_install_directory> --accept_eula 1 --patch_to [quartus|qprogrammer|qemb|pta] # An example to patch Quartus Prime Pro Edition Software v25.3: quartus-25.3-0.27-windows.exe --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 # An example to patch the Standalone Programmer for Quartus Prime Pro Software v25.3: quartus-25.3-0.27-windows.exe --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 --patch_to qprogrammer For Linux machines: Download and unzip the Quartus Prime Pro version zip file that matches your Quartus Prime Pro version from this KDB. Ensure you run chmod +x on the file ending with linux.run. Run in the command line: ./<installation_patch_run_file>. When GUI pops up, press Next. Note that the GUI may look slightly different depending on the version of Quartus you are using. Accept the license agreement Specify the directory where the patch needs to be applied which may be a different location than Quartus install if you have standalone tools in a different directory from your Quartus Prime Pro software installation. Keep “Allow Patch to be uninstalled” selected. Select the software in which to install the patch: The patch will install in the directory of the software or tool you have selected. You will see an uninstall directory for the patch in your software or tool folder where patch installed; it will contain an executable to uninstall the patch if required for any reason. To confirm patch is installed, you can run ./quartus_sh -v or corresponding version command for your tool via command line. Alternatively, you can Open Quartus in the GUI and select Help → About Quartus Prime in the main menu. If you are opening up a standalone tool you will navigate to Help-> About <tool_name>. For the Command Line Implementation of the patch in Linux, use the following command: ./<patch_filename.run> --mode unattended --installdir <your_install_directory> --accept_eula 1 --patch_to [quartus|qprogrammer|qemb|pta] # An example to patch Quartus Prime Pro Edition v25.3: ./quartus-25.3-0.27-linux.run --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 # An example to patch the Standalone Programmer for Quartus Prime Pro Software v25.3: ./quartus-25.3-0.27-linux.run --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 --patch_to qprogrammer This problem has been fixed in Quartus® Prime Pro Edition Software version 26.1. The below table lists the patches that are available and the associated patch number. The patch zip files are attached to the KDB below: Quartus Prime Pro Edition Version Patch Number 23.3 0.52 23.4 0.70 23.4.1 1.01 24.1 0.52 24.2 0.64 24.3 0.35 24.3.1 1.29 25.1 0.36 25.1.1 1.31 25.3 0.27 25.3.1 1.02Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.
Why are Non-Fatal PCIe* errors logged in Advanced Error Reporting (AER) when using the Intel® FPGA P-Tile/H-Tile , Avalon® Streaming and Avalon® Memory Mapped IP for PCI Express*?
Description The P-Tile/H-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* and the P-Tile/H-Tile Avalon® Memory Mapped Intel® FPGA IP for PCI Express* implements optional Alternative Routing-ID Interpretation (ARI) capability when Multi-function or Single Root I/O Virtualization (SR-IOV) features are enabled. ARI capability includes a field called next function number to help the host BIOS to perform the enumeration process. When ARI is enabled and the number of Physical Functions (PFs) is less than 8 for P-Tile, or 4 for H-tile, the next function number incorrectly shows a value of PF 1. As a result, the following error status bits in the endpoint may get set if AER is enabled, as the Root Port issues a configuration request to the non-existing PF pointed to by the incorrect next function number: Correctable Error Detected (Device Status Register) Unsupported Request Detect (Device Status Register) Advisory Non-Fatal Error Status (Correctable Error Status Register) Unsupported Request Error Status (Uncorrectable Error Status Register) Only set if Advisory Non-Fatal Error Mask bit is set to ‘0’ (Correctable Error Mask Register) An ERR_COR message will be sent to the Root Port if AER is enabled by setting the following bits below: Advisory Non-Fatal Error Mask is set to '0' (Correctable Error Mask Register) Correctable Error Reporting Enable is set to '1' (Device Control Register) Unsupported Request Reporting Enable is set to '1' (Device Control Register) In the Root Port, the following bit will be set if Completion with Unsupported Request status is received Received Master Abort (Secondary Status Register) Also, in the Root Port, the following bit will be set if ERR_COR is received, and AER is enabled ERR_COR Received (Root Error Status Register) Resolution For the P-Tile/H-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* and For the P-Tile/H-Tile Avalon® Memory Mapped Intel® FPGA IP for PCI Express*, software can ignore the detected errors each time enumeration is done. If the following error status bits are set in the endpoint after enumeration, then it is safe for the software to ignore them: Correctable Error Detected (Device Status Register) Unsupported Request Detect (Device Status Register) Advisory Non-Fatal Error Status (Correctable Error Status Register) Unsupported Request Error Status (Uncorrectable Error Status Register) Only if Advisory Non-Fatal Error Mask bit (Correctable Error Mask Register) is set to ‘0’ For simplicity, the workaround can be done in the following order Upon enumeration complete, clear the error registers below (all bits irrespectively) for all PCIe Endpoint Functions Device Status Register Correctable Error Status Register Uncorrectable Error Status Register Clear the error registers below (all bits irrespectively) for the PCIe Root Port related to the PCIe Endpoint Functions above Secondary Status Register Root Error Status Register Repeat step 1 and step 2 for each PCI enumeration process. If runtime polling for errors is being performed, bits 'Correctable Error Detected', 'Unsupported Request Detect', 'Advisory Non-Fatal Error Status' and 'Unsupported Request Error Status' can be checked by the polling software to differentiate this issue from other reliability errors. If only those 4 bits are set, we can assume the errors on the endpoints are related to the P-Tile/H-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* or the P-Tile/H-Tile Avalon® Memory Mapped Intel® FPGA IP for PCI Express* issue and it is appropriate to proceed to clear the error status bits listed in step 1 and step 2 above. For P-Tile, user logic can use the Configuration Intercept Interface (CII) to correctly advertise the ARI next function number when a Configuration Read is issued by the Root Port.Why is the data out of my RAM delayed by an extra clock cycle?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1, you may see the data out of your RAM is delayed by a clock cycle. This problem occurs when the RAM block type is set to AUTO, the Clock Enable is connected, and the RAM has been implemented as an MLAB. This problem only affects Intel® Stratix® 10 devices. Resolution To work around this problem, set the RAM block type to M20K or do not connect the Clock Enable. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Why don’t I get a programming file when I compile with the Quartus® Prime Pro Edition software version 25.1.1?
Description Beginning with version 25.1.1 of the Quartus® Prime Pro Edition software, pin location assignments and I/O standard assignments are required for a programming file to be generated. If these required assignments are missing, no programming file is generated. You must add the required assignments and recompile your design to generate a programming file. If you do not want to generate a programming file, you may ignore this behavior change. To determine whether your design is missing pin location or I/O standard assignments, review your compilation messages. If either of the following messages was generated during your compile, your design is missing pin location or I/O standard assignments that are required to generate a programming file: Critical Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Critical Warning: No exact pin location assignment(s) for <number> pins of <number> total pins. For the list of pins, please refer to the I/O Assignment Warnings table in the fitter report Resolution Review the I/O Assignment Warnings report, found in the Place sub-section of the Fitter section of the compilation report. Alternately, review the <revision>.fit.plan.rpt report file. For any pins in the I/O Assignment Warnings report that are reported as “Missing location assignment” or “Missing I/O standard,” add the appropriate location or I/O standard assignment. For help making these assignments, refer to Assigning I/O Pins After adding any required assignments, recompile the design to generate a programming file. This change applies to all device families supported by the Quartus® Prime Pro Edition software, beginning in version 25.1.1. Missing pin location or I/O standard assignments are reported as a critical warning, not an error. If you script the compilation of projects, the exit code of the compilation process still indicates success even if pin location or I/O standard assignments are missing, because missing pin location or I/O assignments are reported as a critical warning, not an error.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).Why are UnsupReq, NonFatalErr, and CorrErr statuses asserted after power cycle or OS reboot while using the P-Tile Intel® FPGA IP for PCI Express?
Description You may find UnsupReq, NonFatalErr, and CorrErr status asserted after power cycle or operating system (OS) reboot when using the P-Tile Intel® FPGA IP for PCI Express. Resolution According to the PCI Express Base specification revision 4.0 version 1.0, during the enumeration of a non-existent device or function, completion with UR status is sent, and UnsupReq is asserted. Meanwhile, Non-Fatal Advisory Error is determined, and CorrErr and NonFatalErr are asserted. To work around this problem, clear the UnsupReq, NonFatalErr, and CorrErr statuses in the PCI Express configuration space registers before checking them during data transactions. This problem is not planned to be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.Why does the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example may fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled. Resolution To work around this problem in the Intel® Quartus® Prime Pro Software version 22.1 and earlier, launch the Design Space Explorer II in the Intel® Quartus® Prime Pro Software and perform seed sweeps. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.When does the Quartus® Prime Design Software, IP cores, and Questa*-Altera® FPGA Edition Software check out a license?
Description Below is a description of how the Quartus® Prime Design Software, IP cores, and Questa*-Altera® FPGA Edition Software utilize licenses: Resolution Quartus® Prime Design Software: All Quartus® Prime Design Software processes check for a valid license, including the Quartus® GUI, Analysis & Synthesis, Assembler, and TimeQuest Timing Analyzer. These processes start only if a valid license is available. They do not hold or occupy the license; they only validate that one is available. However, the Fitter checks out a license when it starts and holds it for the duration of the Fitter process. IP cores: A license for an IP core is checked out when the Quartus® Prime Design Software opens the first encrypted file of the IP core for synthesis. This license is held for the duration of synthesis. The Assembler checks out the license for every IP core to create the programming file and holds it for the duration of the Assembler process. Questa*-Intel® FPGA Edition software: Once Questa*-Intel® FPGA Edition Software loads a design unit during elaboration, a Questa-Intel® FPGA Edition license is checked out. It remains checked out until the simulation ends (quit -sim), or the simulator is closed. Once a waveform is loaded into the simulator, a Questa*-Intel® FPGA Edition Software license is also checked out for viewing Wave Log Format File (.wlf), and it remains checked out until the waveform window is closed. Related Articles What happens to a license if the Quartus II software terminates unexpectedly? Can I perform multiple compilations using the Quartus II software at the same time on one computer with a one seat floating license or one fixed (node locked) license file?Why is '256-bit' the only option available for the 'Application Interface Width' parameter of the L-tile and H-tile Avalon® Memory mapped Intel® FPGA IP for PCI Express*
Description Starting with the Intel® Quartus® Prime Pro Edition Software version 21.4, the '64-bit' option for the 'Application Interface Width' parameter of the L-tile and H-tile Avalon® Memory mapped Intel® FPGA IP for PCI Express* is no longer available. Resolution To migrate an L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* instance from a '64-bit' 'Application Interface Width' configuration to a '256-bit' 'Application Interface Width' configuration. Open the Platform Designer system where the L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* is instantiated. Under the 'System Settings' tab make the following changes: Set the 'Application Interface Width' parameter to '256-bit'. Set the 'Hard IP Mode' parameter to the same configuration but using a '256-bit' interface. Under the 'Avalon-MM Settings' tab make the following changes: Set the 'Avalon-MM address width' to '64-bit'. If the 'Enable non-bursting Avalon-MM Slave interface with individual byte access (TXS)' parameter is set to 'ON', adjust the 'Address width of accessible PCIe memory space (TXS)' to accommodate the new address range of the system. Go to the 'System' menu and select the 'Assign Base Address' option. Platform Designer will rearrange the system address map to accommodate the changes. Save the Platform Designer system. Regenerate the Platform Designer system.
