Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench fail to simulate correctly in the supported Siemens* QuestaSim* 2021.4 or later versions?
Description Due to a compatibility problem between version 22.3 and later of the Intel® Quartus® Prime Software and the Siemens* QuestaSim* 2021.4, 2022.4 tool, simulation of the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench will fail to simulation correctly with the following errors: # INFO: 116032 ns RP User Avmm Driver: begin RP Configuration. # FATAL: Simulation stopped due to inactivity! # FAILURE: Simulation stopped due to Fatal error! # FAILURE: Simulation stopped due to error! Resolution To work around this problem, use Siemens* Questa Sim-64 2022.2. Starting in the Intel® Quartus® Prime Software version 23.3, solve this issue by adding this command " set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" before running simulation in the Siemens* Questa Sim.How is the Intel® Stratix® 10 DDR4 IP chip select signals mapped for the top and bottom memory devices in a clamshell topology?
Description When the clamshell topology is enabled in the Intel® Stratix® 10 DDR4 IP Parameter Editor, each rank requires two CS pins to configure the top and bottom memory chips separately. The following content shows how to map the CS pins from FPGA to memory chips in single-rank and dual ranks designs. Resolution For single-rank components: The Top (non-mirrored) components, FPGA_CS0, goes to MEM_TOP_CS0 The bottom (mirrored) components, FPGA_CS1, goes to MEM_BOT_CS0 For Dual-Rank components: The Top (non-mirrored) components, FPGA_CS0 goes to MEM_TOP_CS0 and FPGA_CS1 goes to MEM_TOP_CS1 The bottom (mirrored) components, FPGA_CS2 goes to MEM_BOT_CS0 and FPGA_CS3 goes to MEM_BOT_CS1Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see the following error when compiling Intel® Stratix® 10 designs containing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP: Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4 This error might occur if the reference clocks for the HBM2 intellectual property (IP) are set as virtual pins. Resolution To work around this error, ensure that the reference clocks for the HBM2 IP do not have a virtual pin assignment. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Why does the HDMI FPGA IP Design Example fail to generate when selecting the board option to Custom Development Kit?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the following error will appear when generating HDMI FPGA IP Design Example when selecting the board option to Custom Development Kit: Tcl error: ERROR: Value "OSC_CLK_1_" for "DEVICE_INITIALIZATION_CLOCK" assignment is illegal. Specify a legal value. Resolution To work around this problem, please follow the steps below: Users can select the No Development Kit option instead of Custom Development Kit. The generated design will remain the same, but the user must update the PIN assignment in the QSF file. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.1.CMake Error: LIBUDEV_LIBRARIES variables are used in this project, but they are set to NOTFOUND.
Description When you build the Open Programmable Acceleration Engine (OPAE) SDK source code using a development branch and pack it into several local RPM packages, the following error might occur: CMake Error: The following variables are used in this project, but they are set to NOTFOUND. Please set them or make sure they are set and tested correctly in the CMake files: LIBUDEV_LIBRARIES linked by target "fpgaperf_counter" in directory /home/diankun/opae-sdk/external/opae-legacy/tools/fpgaperf_counter -- Configuring incomplete, errors occurred! See also "/home/XXX/opae-sdk/build/CMakeFiles/CMakeOutput.log". See also "/home/XXX/opae-sdk/build/CMakeFiles/CMakeError.log". Resolution To work around this problem, you should add “-DOPAE_LEGACY_TAG=<tag>” and “-DOPAE_SIM_TAG=<tag>” into your compile command. eg: cmake .. -DCPACK_GENERATOR=RPM -DOPAE_BUILD_LEGACY=ON -DOPAE_BUILD_EXTRA_TOOLS_FPGABIST=ON -DOPAE_BUILD_SIM=ON -DOPAE_LEGACY_TAG=2.0.10-2 -DOPAE_SIM_TAG=2.0.10-2Why do I see different Stratix® 10 Quartus® Prime Pro Edition Software generated DDR4 IBIS pin model at same bus signals ?
Description This is expected in the DDR4 IBIS model generated from Quartus® Prime Pro Edition Software. The IBIS model is based on pin location and function in the design. In the x8/9 design, some of the DQ or Address/Command pins are located on a pin supporting DQS functionality (in x4 interfaces). The physical properties of the I/O pins that support both DQ and DQS functions are slightly different than the pins that only support DQ functions, so Quartus® Prime Pro Edition Software uses different models to improve the accuracy of the simulation. Resolution This is an example DDR4 IBIS model generated from Quartus® Prime Pro Edition Software. You can see the mem_a(14) and mem_a(13) pins are assigned to the DQS functionality pin and have a different IBIS model name than other mem_a pins. mem_a(14)~pad sstl12_rtio_r34cp1_dqs_lv mem_a(13)~pad sstl12_rtio_r34cp1_dqs_lv mem_a(12)~pad sstl12_rtio_r34cp1_lv mem_a(16)~pad sstl12_rtio_r34cp1_lv mem_a(15)~pad sstl12_rtio_r34cp1_lv mem_a(2)~pad sstl12_rtio_r34cp1_lv mem_a(6)~pad sstl12_rtio_r34cp1_lv mem_a(0)~pad sstl12_rtio_r34cp1_lv mem_a(3)~pad sstl12_rtio_r34cp1_lv mem_a(7)~pad sstl12_rtio_r34cp1_lv mem_a(1)~pad sstl12_rtio_r34cp1_lvWhy can't QSPI flash be accessed using the Mailbox Client Intel® FPGA IP in designs that include HPS?
Description In Intel® Stratix® 10 and Intel Agilex® 7 devices with HPS, due to the implementation of HPS software, once the HPS is released from reset, you cannot access QSPI flash using the Mailbox Client Intel® FPGA IP. You will see error code 0x81 (QSPI_ALREADY_OPEN) for QSPI_OPEN operation (Please refer to Mailbox Client Intel® FPGA IP User Guide for the details of the operation command and error codes). Resolution This is expected behavior. In designs which include HPS, both SDM and HPS cannot access the shared QSPI flash simultaneously.Warning (16817): Verilog HDL warning at altera_xcvr_*_reconfig_parameters.sv: overwriting previous definition of altera_xcvr_*_reconfig_parameters package
Description If your design contains multiple JESD204B IPs with different configurations, you may see the following warning in Intel® Quartus® Prime Pro software version 15.1 or later during Analysis and Synthesis stage. When targetting Intel Stratix® 10 devices: Warning (16817): Verilog HDL warning at altera_xcvr_rcfg_10_reconfig_parameters.sv: overwriting previous definition of module altera_xcvr_rcfg_10_reconfig_parameters When targetting Intel Arria® 10 or Intel Cyclone® 10 GX devices: Warning (16817): Verilog HDL warning at altera_xcvr_native_a10_reconfig_parameters.sv: overwriting previous definition of altera_xcvr_native_a10_reconfig_parameters package If your design does not rely on the *_reconfig_parameters.sv package files for performing transceiver reconfiguration, it is safe to ignore the warning. Resolution If your design must include the reconfiguration packages, ensure the uniqueness of each of the packages by renaming the packages. For example, a design that contains two simplex RX interfaces with different data rates, assign a unique name by changing the package module from: package altera_xcvr_native_a10_reconfig_parameters; To: package altera_xcvr_native_a10_reconfig_parameters_inst1; In the first instance of RX, and changing to another unique name: package altera_xcvr_native_a10_reconfig_parameters_inst2; In the second instance of RX. Then, import those packages into your design per your design requirements.
