Why do I unexpectedly observe intermittent DDM Errors?
Description Beginning January 10, 2026, executing commands in the terminal or GUI of Quartus® Prime Pro Edition software, Quartus Embedded Edition software or select standalone tools may cause the software or tool to crash with an error similar to the crash signature shown below. This error affects: Quartus Prime Pro Software versions v23.3 through v25.3.1 Standalone Quartus Prime Pro Programmer v23.3 through v25.3.1 Standalone Quartus Prime Pro Embedded Edition v25.3 and v25.3.1 Standalone Quartus Prime Pro Power Thermal Analyzer v25.3 through v25.3.1 This issue is not observed in Quartus Prime Pro Edition versions 23.2 or prior or Quartus Prime Standard Edition. Crash Signature: Error (22912): Unhandled exception: Fatal Error: Assertion failed tools/cpp/ddm/ddm_assessor.cpp:53: DDM_T::verify_token(token) : Cannot identify the client from function assertion_error in tools/cpp/ddm_report/ddm_report_msg.cpp@465 *** Fatal Error: Program termination requested *** *** Below is the stack trace at the time the error occurred. *** The lines beginning "Err Handler" represent frames relating *** to generating this report. *** The point at which the error occurred is somewhere after these lines. *** There may be a few frames representing standard/library code *** before the Quartus frames begin. *** The search for the error should begin with the Quartus frames. *** Unwinder: libunwind *** Stack depth: 15 Quartus 0x24e67: err_terminator() + 0x1bc (ccl_err) Quartus 0xb036a: __cxxabiv1::__terminate(void (*)()) + 0xa (stdc++) Quartus 0xb03d5: (stdc++) Quartus 0xb0628: (stdc++) Quartus 0x1680d: void ddm_throw<DDM_RUNTIME_ERROR>(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x26d (ddm_report) Quartus 0x13fae: DDM_REPORT::DDM_ASSERTION_HANDLER::assertion_error(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >) const + 0xde (ddm_report) Quartus 0x12a52: DDM_REPORT::ASSERTION_HANDLER::error(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >) + 0x72 (ddm_report) Quartus 0x13e64: DDM_REPORT::detail::assert_at_line(char const*, char const*, int, char const*, ...) + 0x1b4 (ddm_report) Quartus 0x205fb0: ddm_set_lassessor(DDM_T_ASSESSOR*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x60 (ddm) Quartus 0xf4445: DMS_MANAGER::DMS_MANAGER() + 0x5c5 (dni_dms) Quartus 0xf45b2: DMS_MANAGER::get() + 0x7a (dni_dms) Quartus 0xf6db4: _GLOBAL__sub_I_dms_manager.cpp + 0x58 (dni_dms) Quartus 0x647e: (ld-linux-x86-64) Quartus 0x6568: (ld-linux-x86-64) Quartus 0x202ca: (ld-linux-x86-64) Resolution To work around this problem: For Windows machines Download and unzip the Quartus Prime Pro version zip file that matches your Quartus Prime Pro version from this KDB. Double click on the executable ending in “windows.exe”. When the GUI pops up, press Next. Note that the GUI may look slightly different depending on the version of Quartus you are using. Accept the license agreement Specify the directory where the patch needs to be applied which may be a different location than Quartus install if you have standalone tools in a different directory from your Quartus Prime Pro software installation. Keep “Allow Patch to be uninstalled” selected. Select the software in which to install the patch: The patch will install in the directory of the software or tool you have selected. You will see an uninstall directory for the patch in your software or tool folder where patch is installed; it will contain an executable to uninstall the patch if required for any reason. To confirm patch is installed, you can run quartus_sh -v or corresponding version command for your tool via command line. Alternatively, you can Open Quartus in the GUI and select Help → About Quartus Prime in the main menu. If you are opening up a standalone tool you will navigate to Help-> About <tool_name>. For the Command Line Implementation of the patch in Windows, use the following command: <patch_filename.exe> --mode unattended --installdir <your_install_directory> --accept_eula 1 --patch_to [quartus|qprogrammer|qemb|pta] # An example to patch Quartus Prime Pro Edition Software v25.3: quartus-25.3-0.27-windows.exe --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 # An example to patch the Standalone Programmer for Quartus Prime Pro Software v25.3: quartus-25.3-0.27-windows.exe --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 --patch_to qprogrammer For Linux machines: Download and unzip the Quartus Prime Pro version zip file that matches your Quartus Prime Pro version from this KDB. Ensure you run chmod +x on the file ending with linux.run. Run in the command line: ./<installation_patch_run_file>. When GUI pops up, press Next. Note that the GUI may look slightly different depending on the version of Quartus you are using. Accept the license agreement Specify the directory where the patch needs to be applied which may be a different location than Quartus install if you have standalone tools in a different directory from your Quartus Prime Pro software installation. Keep “Allow Patch to be uninstalled” selected. Select the software in which to install the patch: The patch will install in the directory of the software or tool you have selected. You will see an uninstall directory for the patch in your software or tool folder where patch installed; it will contain an executable to uninstall the patch if required for any reason. To confirm patch is installed, you can run ./quartus_sh -v or corresponding version command for your tool via command line. Alternatively, you can Open Quartus in the GUI and select Help → About Quartus Prime in the main menu. If you are opening up a standalone tool you will navigate to Help-> About <tool_name>. For the Command Line Implementation of the patch in Linux, use the following command: ./<patch_filename.run> --mode unattended --installdir <your_install_directory> --accept_eula 1 --patch_to [quartus|qprogrammer|qemb|pta] # An example to patch Quartus Prime Pro Edition v25.3: ./quartus-25.3-0.27-linux.run --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 # An example to patch the Standalone Programmer for Quartus Prime Pro Software v25.3: ./quartus-25.3-0.27-linux.run --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 --patch_to qprogrammer This issue is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software. The below table lists the patches that are available and the associated patch number. The patch zip files are attached to the KDB below: Quartus Prime Pro Edition Version Patch Number 23.3 0.52 23.4 0.70 23.4.1 1.01 24.1 0.52 24.2 0.64 24.3 0.35 24.3.1 1.29 25.1 0.36 25.1.1 1.31 25.3 0.27 25.3.1 1.02
Error (XXXXX): Cannot generate Atom Netlist File because family Stratix® 10 FPGA is not installed
Description Due to a problem in the FPGA SDK for OpenCL version 21.1, this error may be seen when compiling a Stratix® 10 OpenCL kernel using the import flow. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 21.1. Download and install Patch 0.14cl from the files below. This problem is fixed starting with the Quartus® Prime Pro Edition software version 21.2.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).Error(19433): Transfer between periphery and DSP or RAM (signal name) through logic cell (signal name) will make timing transfer impossible
Description You might get this error message when compiling design connecting External Memory Interfaces Intel® Stratix® 10 FPGA IP to Block RAM directly by using the Intel® Quartus® Prime Pro Edition Software. Resolution You can avoid this error by adding one or more pipeline stages between the External Memory Interfaces Intel® Stratix® 10 FPGA IP and the Block RAM.Why does Linux report "DMA engine initialization failed" error when EMAC uses GMII interface?
Description When supporting GMII interface for HPS EMAC, there are three clocks exported to FPGA: emac_tx_clk_i(input), emac_rx_clk_i(input), emac_gtx_clk(output) The Linux would report below error if the emac_tx_clk_i clock is not connected correctly: ...... [ 4.291414] socfpga-dwmac ff802000.ethernet: Failed to reset the dma [ 4.297785] socfpga-dwmac ff802000.ethernet eth1: stmmac_hw_setup: DMA engine initialization failed [ 4.306806] socfpga-dwmac ff802000.ethernet eth1: stmmac_open: Hw setup failed ...... Resolution Besides connecting the emac_rx_clk_i(125MHz) for GMII, the emac_tx_clk_i also needs to be connected correctly (2.5MHz or 25MHz), although it is not used in GMII mode. The emac_tx_clk_i requirement information has been added in the HPS document beginning with version 21.2.Why can’t I reset the Hard Processor System (HPS) of Intel Agilex® 7 FPGA or Intel® Stratix® 10 FPGA using the Mailbox Client Intel® FPGA IP?
Description You might see the Hard Processor System (HPS) on Intel Agilex® 7 SoC FPGA and Intel® Stratix® 10 SoC FPGA fail to reset when issuing the REBOOT_HPS command (0x47) through the Mailbox Client Intel® FPGA IP. The REBOOT_HPS command is not supported by the FPGA core to Secure Device Manager (SDM) interface, trying to reset the HPS from the FPGA core will be unsuccessful. Resolution To work around this problem, you must issue the command to reset the HPS through the JTAG interface using the System Console packet service as described in the AN 936: Executing SDM Commands via JTAG Interface. Extract the contents of the sdm-commands.zip. Open System Console from the Intel® Quartus® Prime Pro Edition Software by clicking Tools -> System Debugging Tools -> System Console. In the terminal window of System Console, change directories to where the file sdm_command.tcl was extracted. Enter the following command: % source sdm_command.tcl Execute the REBOOT_HPS command (0x47) with the exec_command procedure: % exec_command 0x47 The Intel Agilex 7 Hard Processor Technical Reference Manual and Intel Stratix 10 Hard Processor System Technical Reference Manual are scheduled to be updated with the above information.Why don’t I get a programming file when I compile with the Quartus® Prime Pro Edition software version 25.1.1?
Description Beginning with version 25.1.1 of the Quartus® Prime Pro Edition software, pin location assignments and I/O standard assignments are required for a programming file to be generated. If these required assignments are missing, no programming file is generated. You must add the required assignments and recompile your design to generate a programming file. If you do not want to generate a programming file, you may ignore this behavior change. To determine whether your design is missing pin location or I/O standard assignments, review your compilation messages. If either of the following messages was generated during your compile, your design is missing pin location or I/O standard assignments that are required to generate a programming file: Critical Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Critical Warning: No exact pin location assignment(s) for <number> pins of <number> total pins. For the list of pins, please refer to the I/O Assignment Warnings table in the fitter report Resolution Review the I/O Assignment Warnings report, found in the Place sub-section of the Fitter section of the compilation report. Alternately, review the <revision>.fit.plan.rpt report file. For any pins in the I/O Assignment Warnings report that are reported as “Missing location assignment” or “Missing I/O standard,” add the appropriate location or I/O standard assignment. For help making these assignments, refer to Assigning I/O Pins After adding any required assignments, recompile the design to generate a programming file. This change applies to all device families supported by the Quartus® Prime Pro Edition software, beginning in version 25.1.1. Missing pin location or I/O standard assignments are reported as a critical warning, not an error. If you script the compilation of projects, the exit code of the compilation process still indicates success even if pin location or I/O standard assignments are missing, because missing pin location or I/O assignments are reported as a critical warning, not an error.Error (18939): Unexpected error in JTAG server: Different TAPS selected
Description You may see this error when configuring Intel® Stratix® 10 SoC devices using Intel® Quartus® Prime Programmer or quartus_pgm if the FPGA JTAG and HPS JTAG are chained. When chained internally, the HPS will appear at device index 1 and the FPGA will be at device index 2. Resolution To avoid this error, ensure you target the appropriate device in the chain. Prior to programming. you can identify the device position in the JTAG chain by clicking on Auto-Detect in the Intel® Quartus® Prime Programmer GUI or running jtagconfig in the command line.How do I extend Windows* Server 2016 file path support from 260 to to 1024 characters?
Description Windows* Server 2016 supports file paths up to 260 characters by default. From build 1607, Windows Server 2016 now supports longer paths up to 1024 characters with the proper registry configuration. The Intel® Quartus® Prime Pro Edition Software can now support file paths up to 1024 characters when Windows Server 2016 registry is correctly configured. Resolution To configure your Windows* Server 2016 system registry to support long file paths, follow these steps: Verify or edit the Registry settings to support long paths: a) Open the Registry Editor (Press Windows* Key and type regedit and press Enter key) b) Navigate to HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem c) Change the LongPathsEnabled value to 1. If you do not see LongPathsEnabled listed, you must create the entry by right-clicking the FileSystem key, choosing New > DWORD (32-bit) Value, and then naming the new value LongPathsEnabled. Verify or edit any Group Policy to support long paths: a) Open Group Policy Editor* (Press Windows Key and type gpedit.msc and hit Enter key) b) Navigate to the following directory: Local Computer Policy > Computer Configuration > Administrative Templates > System > Filesystem > NTFS. c) Click Enable NTFS long paths option and enable it. These changes have been verified with Intel® Quartus® Prime Pro and Windows* Server 2016 build 1607 only. Other Windows OS, such as Windows 10 have not been verified.Why are Non-Fatal PCIe* errors logged in Advanced Error Reporting (AER) when using the Intel® FPGA P-Tile/H-Tile , Avalon® Streaming and Avalon® Memory Mapped IP for PCI Express*?
Description The P-Tile/H-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* and the P-Tile/H-Tile Avalon® Memory Mapped Intel® FPGA IP for PCI Express* implements optional Alternative Routing-ID Interpretation (ARI) capability when Multi-function or Single Root I/O Virtualization (SR-IOV) features are enabled. ARI capability includes a field called next function number to help the host BIOS to perform the enumeration process. When ARI is enabled and the number of Physical Functions (PFs) is less than 8 for P-Tile, or 4 for H-tile, the next function number incorrectly shows a value of PF 1. As a result, the following error status bits in the endpoint may get set if AER is enabled, as the Root Port issues a configuration request to the non-existing PF pointed to by the incorrect next function number: Correctable Error Detected (Device Status Register) Unsupported Request Detect (Device Status Register) Advisory Non-Fatal Error Status (Correctable Error Status Register) Unsupported Request Error Status (Uncorrectable Error Status Register) Only set if Advisory Non-Fatal Error Mask bit is set to ‘0’ (Correctable Error Mask Register) An ERR_COR message will be sent to the Root Port if AER is enabled by setting the following bits below: Advisory Non-Fatal Error Mask is set to '0' (Correctable Error Mask Register) Correctable Error Reporting Enable is set to '1' (Device Control Register) Unsupported Request Reporting Enable is set to '1' (Device Control Register) In the Root Port, the following bit will be set if Completion with Unsupported Request status is received Received Master Abort (Secondary Status Register) Also, in the Root Port, the following bit will be set if ERR_COR is received, and AER is enabled ERR_COR Received (Root Error Status Register) Resolution For the P-Tile/H-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* and For the P-Tile/H-Tile Avalon® Memory Mapped Intel® FPGA IP for PCI Express*, software can ignore the detected errors each time enumeration is done. If the following error status bits are set in the endpoint after enumeration, then it is safe for the software to ignore them: Correctable Error Detected (Device Status Register) Unsupported Request Detect (Device Status Register) Advisory Non-Fatal Error Status (Correctable Error Status Register) Unsupported Request Error Status (Uncorrectable Error Status Register) Only if Advisory Non-Fatal Error Mask bit (Correctable Error Mask Register) is set to ‘0’ For simplicity, the workaround can be done in the following order Upon enumeration complete, clear the error registers below (all bits irrespectively) for all PCIe Endpoint Functions Device Status Register Correctable Error Status Register Uncorrectable Error Status Register Clear the error registers below (all bits irrespectively) for the PCIe Root Port related to the PCIe Endpoint Functions above Secondary Status Register Root Error Status Register Repeat step 1 and step 2 for each PCI enumeration process. If runtime polling for errors is being performed, bits 'Correctable Error Detected', 'Unsupported Request Detect', 'Advisory Non-Fatal Error Status' and 'Unsupported Request Error Status' can be checked by the polling software to differentiate this issue from other reliability errors. If only those 4 bits are set, we can assume the errors on the endpoints are related to the P-Tile/H-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* or the P-Tile/H-Tile Avalon® Memory Mapped Intel® FPGA IP for PCI Express* issue and it is appropriate to proceed to clear the error status bits listed in step 1 and step 2 above. For P-Tile, user logic can use the Configuration Intercept Interface (CII) to correctly advertise the ARI next function number when a Configuration Read is issued by the Root Port.
