Error(19433): Transfer between periphery and DSP or RAM (signal name) through logic cell (signal name) will make timing transfer impossible

Description

You might get this error message when compiling design connecting External Memory Interfaces Intel® Stratix® 10 FPGA IP to Block RAM directly by using the Intel® Quartus® Prime Pro Edition Software.

Resolution

You can avoid this error by adding one or more pipeline stages between the External Memory Interfaces Intel® Stratix® 10 FPGA IP and the Block RAM.