Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.What is the AC coupling capacitor recommendation for E-tile reference clock input?
Description It is recommended to add external AC coupling capacitors given the E-tile reference clock input buffer structure. Resolution There are two internal 50ohm terminations that will act as 100ohm parallel termination. See the Intel® Stratix® 10 TX Signal Integrity Development Kit for an example of these capacitors. Please refer to E-Tile Transceiver PHY User Guide Figure 64. IO Pad Ring - Transceiver Reference Clock Input Pad.Why does Aldec Riviera-PRO simulation fail/hang using the PHY Lite for Parallel Interfaces Intel® FPGA IP design example?
Description If PHY Lite for Parallel Interfaces Intel® FPGA IP design example is generated using the Intel® Quartus® Prime Pro Edition Software version 21.1 or 21.2, you will encounter the Aldec Riviera-Pro simulation hang or fail to simulate. This problem was root caused in the Aldec Riviera-Pro version 2020.04, which the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2 generates simulation files for. Resolution This problem has been resolved in Aldec Riviera-PRO version 2021.4, which is supported in the Intel® Quartus® Prime Pro Edition Software version 21.3 and onwards. Regenerate your design with the updated Intel Quartus software version.Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see the following error when compiling Intel® Stratix® 10 designs containing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP: Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4 This error might occur if the reference clocks for the HBM2 intellectual property (IP) are set as virtual pins. Resolution To work around this error, ensure that the reference clocks for the HBM2 IP do not have a virtual pin assignment. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Why does the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench fail to simulate correctly in the supported Siemens* QuestaSim* 2021.4 or later versions?
Description Due to a compatibility problem between version 22.3 and later of the Intel® Quartus® Prime Software and the Siemens* QuestaSim* 2021.4, 2022.4 tool, simulation of the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench will fail to simulation correctly with the following errors: # INFO: 116032 ns RP User Avmm Driver: begin RP Configuration. # FATAL: Simulation stopped due to inactivity! # FAILURE: Simulation stopped due to Fatal error! # FAILURE: Simulation stopped due to error! Resolution To work around this problem, use Siemens* Questa Sim-64 2022.2. Starting in the Intel® Quartus® Prime Software version 23.3, solve this issue by adding this command " set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" before running simulation in the Siemens* Questa Sim.Why does the design example generation fail when upgrading from Intel® Quartus® Prime Software v21.3 and earlier to v21.4 of the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express?
Description Due to a known problem, the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express design example generation will fail if the base IP has been upgraded from Intel® Quartus® Quartus Prime Software v21.3 and earlier to v1.4. Resolution When using version 21.4 of the Intel® Quartus® Prime Pro Edition Software, a clean non-upgraded version of the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP must be used. This problem has been fixed starting with the 22.1 version of the Intel® Quartus® Prime Pro Edition Software.Why does a kernel panic occur when OpenCL™ Applications are executed on Intel® FPGA Development Kits with IOMMU support enabled?
Description When executing OpenCL™ host applications on an attached development kit while IOMMU (e.g. intel_iommu) is enabled in a Linux Kernel, a kernel panic may occur and cause the host to hang. This may happen even if 'aocl diagnose' and 'aocl program' pass. The hang occurs because the OpenCL™ board support packages (BSPs) for the development kits don't support SR-IOV. Resolution To work around this problem, disable IOMMU functionality : For example on CentOS7.4, with grub2, UEFI and intel_iommu : 1. Edit /etc/default/grub and delete the following line. intel_iommu=on in GRUB_CMDLINE_LINUX 2. Update grub configuration file grub2-mkconfig -o /boot/efi/EFI/centos/grub.cfg 3. Reboot 4. Check /proc/cmdline Ensure intel_iommu=on does not appear on the kernel command line. This workaround does not apply to the Intel FPGA Programmable Acceleration Card (PAC) since that OpenCL™ BSP does support SR-IOV. If IOMMU is disabled when using the PAC, refer to the Intel® Acceleration Stack Quick Start Guide for instructions to enable the Intel IOMMU driver.Compiler Error: Argument in 'constant' address space cannot be stored in heterogeneous global memory.
Description Due to a problem in the Intel® FPGA SDK for OpenCL version 19.2, this error may be seen when compiling an OpenCL kernel targeting heterogeneous global memory using Stratix 10® MX devices. Resolution This problem is fixed beginning with the Intel® FPGA SDK for OpenCL software version 19.3.error: Unexpected use of HDL library function(s) (possibly due to taking the address of the function)!
Description You may see this error message when the Intel® FPGA SDK for OpenCL™ compiler executes an EFI(Extensible Firmware Interface) function which is equivalent to its OpenCL funtion Resolution This problem is fixed beginning with the Intel FPGA SDK for OpenCL compiler software version 18.1.
