Why does refclk_fgt_enabled_i in the F-Tile Reference and System PLL Clocks IP fail to assert even after in_refclk_fgt_i is active and stable and en_refclk_fgt_i is asserted?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1.1 and earlier, you might observe refclk_fgt_enabled_i in the F-Tile Reference and System PLL clocks IP fail to lock. Background: When the FGT PMA reference clock source is not active at configuration, then you must unselect below parameter: And the F-Tile Reference and System PLL Clocks FPGA IP will expose below control and status signals for each FGT PMA: en_refclk_fgt_i refclk_fgt_enabled_i Expected behavior: For each FGT PMA, after its reference clock source #i is active, then we can drive en_refclk_fgt_i to get refclk_fgt_enabled_i asserted. Root Cause: During support logic generation, Quartus creates a shared AVMM arbiter for the F-Tile Reference and System PLL Clocks IP internal datapath AVMM master and the F-Tile protocol IP datapath AVMM masters. In certain corner cases, the internal datapath AVMM master of the F-Tile System PLL IP is connected to a different reconfiguration clock source than the one used by the F-Tile protocol IP datapath AVMM masters. This clock mismatch causes the shared AVMM arbiter to malfunction, resulting in failed datapath AVMM transactions. As a result, the F-Tile System PLL IP internal state machine cannot complete its initialization sequence, and refclk_fgt_enabled_i remains deasserted. Resolution To work around this problem, you can apply below methods: For Quartus® Prime Pro Edition Software version 25.1.1, apply patch 1.53. For other Quartus® Prime Pro Edition Software versions, disable the F-Tile protocol IP datapath AVMM interface. As a result, no shared AVMM arbiter is generated between the F-Tile protocol IP datapath AVMM masters and the internal datapath AVMM master of the F-Tile System PLL IP. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.Why does the Quartus® Prime Pro Edition software version 26.1.1 report Error (25640) when an Agilex® 5 FPGA GTS regional reference clock drives 16 transceiver channels?
Description In the Quartus® Prime Pro Edition software version 26.1, an Agilex® 5 FPGA D series transceiver design may compile when a single GTS regional reference-clock pin drives 16 transceiver channels across four GTS quads. Starting with the Quartus Prime Pro Edition software version 26.1.1, the Fitter reports Error (25640) for the reference-clock input. The error indicates that the reference clock drives 16 transceiver channels, exceeding the allowed limit of 12 channels. The same user RTL, SDC, and pin assignments can therefore compile in version 26.1 and fail in version 26.1.1. Resolution This is expected behavior and is consistent with Section 2.6.1, “Reference Clock Network,” of the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs (Document 817660). Therefore, a regional reference-clock pin must not drive transceiver channels in four GTS quads. Because each GTS quad contains four transceiver channels, one reference-clock pin can drive a maximum of three quads, or 12 transceiver channels. To use 16 transceiver channels on one shoreline, provide at least two regional reference-clock pins, or a regional pin plus a local pin on the unreachable quad, so that no pin drives more than three GTS quads.Why does the Low Latency 40G Ethernet IP drop non-PTP packets when PTP residence-time update is enabled?
Description Due to a problem in the Quartus® Standard Edition software version 21.1, you may see the Low Latency 40G Ethernet IP may drop large non-PTP packets when the tx_etstamp_ins_ctrl_residence_time_update (PTP residence-time update) is asserted. This problem is typically observed with jumbo frames of approximately 3000 bytes or larger. The affected packets may be counted at the RX interface but may not appear at the TX output. PTP packets themselves may continue to transmit correctly. This problem is not observed when tx_etstamp_ins_ctrl_residence_time_update (PTP residence-time update) is kept deasserted. Resolution A patch (21.1std patch 0.16std) is available to fix this problem for the Quartus Standard Edition Software version 21.1. To request the patch, contact your local Altera support representative. This problem is resolved in the Quartus Prime Pro Edition Software 26.1. Altera recommends migrating to the latest Quartus Prime Pro Edition Software to address this problem.Why can't Symmetric Cryptographic Accelerator (SCA) support be enabled on Agilex® 7 NL[HZ3.1] OPN Devices with AGIC, AGID, AGFC, or AGFD Prefixes in Quartus® Prime Pro Edition Software Version 26.1.1?
Description Agilex® 7 NL OPN devices with prefixes of AGIC, AGID, AGFC, AGFD containing Hard Crypto Blocks (also referred to as the Symmetric Cryptographic Accelerator or SCA) are not supported by Quartus Prime Pro Edition Software version 26.1.1. Although the affected NL OPN devices contain SCA hardware, the Quartus® Prime Pro Edition software version 26.1.1 does not allow users to enable or use the SCA functionality on these devices. This is a restriction in Quartus Prime Pro Edition software version 26.1.1 as the SCA enablement was not completed for NL OPNs. Resolution A general workaround is not available in the Quartus Prime Pro Edition software version 26.1.1. Users requiring SCA support on affected Agilex® 7 FPGA F-Series, I-Series with prefixes of NL OPN as AGIC, AGID, AGFC, AGFD devices may request a patch through Altera support channels where applicable. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why do I see RRESP=2 if ECC is enabled in External Memory Interfaces (EMIF) IP?
Description When ECC is enabled in External Memory Interfaces (EMIF) IP of Agilex® 7 FPGA M-Series, Agilex® 5 FPGA, and Agilex® 3 FPGA devices, you might receive RRESP=2 during data readback if any of the following conditions is true. DDR4 Component: Data size of the first write command to the associated AXI4 address ≠ 256 bits * N DDR5 Component/DDR5 DIMM/LPDDR4/LPDDR5: Data size of the first write command to the associated AXI4 address ≠ (Channel DQ width * 16) * N where N is a positive integer (1, 2, 3, ...). The hard memory controller uses fixed DQ burst length. The above conditions generate partial access to the memory. The uninitialized portion of data in the memory will cause uncorrectable ECC error, leading to RRESP=2. Below are some example scenarios that showcase this RRESP problem. Example #1: When using a x16+ECC DDR4 Component interface in fabric accessing mode, the first write command to an AXI4 address is a partial access with the use of WSTRB. WDATA width = 256 bits, AWLEN = 0, WSTRB = 0x0000FFFF: Data size of the first write command to the associated AXI4 address = 128 bits Example #2: When using a 1chx32 LPDDR5 interface with in-line ECC enabled in fabric accessing mode, the first write command to an AXI4 address has only one WDATA beat. WDATA width = 256 bits, AWLEN = 0: Data size of the first write command to the associated AXI4 address = 256 bits Channel DQ width * 16 = 512 bits Example #3: When using a x32+ECC DDR5 RDIMM interface in 256-bit NoC accessing mode, the first write command to an AXI4 address uses an even number AWLEN value. WDATA width = 256 bits, AWLEN = 2: Data size of the first write command to the associated AXI4 address = 768 bits Channel DQ width * 16 = 512 bits Resolution To work around this problem, ensure the data size of the first write command to the associated AXI4 address equals to either 256 bits * N or (Channel DQ width * 16) * N, depending on the memory protocol. An alternative method is available starting with Quartus® Prime Pro Edition Software version 26.1.1. When IP parameter Initialize Memory in the Advanced Calibration Settings section is enabled, on calibration passing, and before handing off control of the memory to user logic, the memory will be initialized with all zeros in the data section and the corresponding ECC codes in the ECC section. With this approach, there is no special requirement on the data size of the first write command to the associated AXI4 address. Note: To avoid leading to long simulation time, only the first 256 bytes of memory will be initialized in simulation when Initialize Memory is enabled. Additional Information DDR4 DIMM interface and LPDDR5 interface using link ECC are not affected by this RRESP problem.Why do I see this warning message after enabled Transceiver Toolkit Debugging Features in GTS SDI II Serial Loopback Design Example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, you will observe below. “warning check failed! > warning: no path is found satisfying assignment" “set_max_skew -from get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|in_wr_ptr_gray -to get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|write_crosser|sync.u|din_s1 -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 - This assignment will be ignored.” It happens when user enables the Transceiver Toolkit Debugging Features in GTS SDI II Serial Loopback Design Example. This problem happens due to the undefined path of the dc_fifo.sdc. Resolution This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why am I seeing High Severity DA warning: "Multiple Clock Domains Driving a Synchronizer Chain" after enabled Transceiver Toolkit in Dual-Simplex Parallel loopback Design Example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, you may see a DA warning: "Multiple Clock Domains Driving a Synchronizer Chain" in the compilation report for the GTS SDI II Dual-Simplex Parallel Loopback design example when the transceiver toolkit is enabled. Resolution This DA Warning can be ignored in 26.1.1, and this problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Error message received from device : Internal error. (subcode 0x001A, Info 0x00000000, Location 0x0000701D )
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1.1, you might encounter this error while configuring new signed and encrypted Partial Reconfiguration (PR) persona bitstreams. The problem impacts Agilex® 5 FPGA PR designs enabled for Encryption and Authentication. Resolution This problem will be fixed in a future release of Quartus® Prime Pro Edition Software. No fix is planned in Quartus® Prime Pro Edition Software version 26.1.1. If you encounter this problem, file a ticket through Altera Premier Support (APS) system to requuest a software patch.Error(24244): Found an error when generating the IBIS Output File for board analysis. Refer to "<project_directory>/output_files/xxx.log" for more information
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, you mat see this error when using the EDA Netlist Writer to generate an IBIS Model. This problem occurs when the project includes R-tile or P-tile I/O pins. Resolution This problem has been fixed beginning with version 24.3 of the Quartus® Prime Pro Edition Software.Why is the bus ordering reversed in the Technology Map Viewer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see that the bus ordering is reversed in the Technology Map Viewer. This problem occurs when a design contains a Block Design File (BDF) whose output bus is connected to a SystemVerilog HDL packed array from a top-level SystemVerilog HDL module. For example, the expected mapping in the Technology Map Viewer is: inst0 -> Out[0] inst1 -> Out[1] inst2 -> Out[2] inst3 -> Out[3] However, the actual mapping after compilation in the Technology Map Viewer become: inst0 -> Out[3] inst1 -> Out[2] inst2 -> Out[1] inst3 -> Out[0] Resolution To work around this problem, do one of the following: Convert the BDF file to Verilog HDL or VHDL. Open the BDF file in the Quartus® Prime Standard Edition Software. Select File > Create / Update > Create HDL Design File from Current File. Choose Verilog HDL or VHDL. Replace the original BDF module in the Quartus® Prime Pro Edition Software project with the generated HDL file. Explicitly reorder the bits in the top-level SystemVerilog HDL module by using a SystemVerilog HDL streaming operator in the port connection.
