Why does the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP fail on Window* OS?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP might fail. This problem only occurs on Windows* OS. This problem occurs because the location of quartus_py.exe file has changed but the IP still calls the file from the previous location. Resolution To work around this problem, copy the quartus_py.exe file from <Quartus installation path>\qcore\bin64\quartus_py.exe to <Quartus installation path>\quartus\bin64\quartus_py.exe This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why the pre-code setting doesn't work for F-Tile PMA and FEC Direct PHY IP on FGT channels?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, the pre-code function doesn’t work on FGT channels with F-Tile PMA and FEC Direct PHY IP. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does the typical web server page is not displayed when using binaries created from the HPS Baseline and Legacy System Example Design in Agilex® 5/Agilex® 3 FPGA device in release 25.3.1 and 26.1?
Description Due to a problem in the HPS Baseline and Legacy System Example Design for Agilex® 5 FPGA and Agilex® 3 FPGA devices, the web server application just shows the “It works!” message instead of the typical view, in which it briefly describes the development kit, shows the state of some LEDs, and allows them to be controlled. This problem is observed in Quartus® Prime Pro Edition software version 25.3.1 and 26.1 releases. Resolution There is no workaround for this problem. This problem will be fixed in a future release.How to set current strength for Agilex® 7 FPGA HPS dedicated IO?
Description Due to a problem in Quartus® Prime Edition Software version 25.3.1 and prior, you may see the following error when you set current strength for HPS dedicated IO in qsf file or in assignment editor. Current strength logic option is set to 2/4/6/8mA for pin intel_agilex_hps_0_<IO_name>~pad， but setting is not supported by I/O standard 1.2-V. This problem occurs because HPS dedicated IOs in Agilex™ 7 device are configured to I/O standard 1.2-V by default in Quartus, instead of I/O standard 1.8-V. Resolution To work around this problem, please set the HPS IO to I/O standard 1.8-V in qsf file or in assignment editor, and then set current strength for the pins to make it work.Why does FPGA core configuration fail in HPS early IO release mode of Arria® 10 SoC device?
Description In Arria® 10 SoC device HPS early IO release mode, you may see FPGA core configuration failure when you use the following command to generate core rbf. quartus_cpf --convert --hps -o bitstream_compression=off <sof_file> <rbf_file> This problem occurs because uncompressed core rbf file may be too large to cause configuration failure. Resolution To work around this problem, please use the following command to generate rbf files. quartus_cpf --convert --hps -o bitstream_compression=on <sof_file> <rbf_file>Why do multiple pulses occur on flr_received signals when host do function level reset to an endpoint device of Scalable Switch IP for PCI Express*?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.1 and later, you may see multiple pulses on flr_received signal of Scalable Switch IP in FLR operation. Resolution To work around this problem, you should respond to flr_completed signal for each pulse on flr_received. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does Nios® V/g processor experiences data corruption when it is enabled with TCM and ECC?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 26.1, data corruption might occur in Nios ® V/g processor designs with tightly coupled memory (TCM) and error correction code (ECC). Both features must be enabled to observe this problem. It is caused by an RTL bug in the processor, which renders failure when the processor executes sw (store word), followed by sh (store halfword) or sb (store byte) instructions. For example, # Initially, value of Y is 0x0001CCCC. li t0, 0x12345678 li t1, 0x200A sw t0, 0(Z) # Store 0x12345678 word into Z sh t1, 0(Y) # Store 0x200A into lower half of Y Result Final value of Y Description Expected 0x0001200A Upper-half of Y is preserved as 0x0001, while lower-half of Y is changed to 0x200A. Actual (Data Corruption) 0x1234200A Upper-half of Y is corrupted to 0x1234, while lower-half of Y is changed to 0x200A. The 0x1234 is from the previous Store Word (sw) instruction. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 26.1, apply either one of the solutions below: Disable TCM. Disable ECC. This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software.Why is the Direct‑to‑Factory Image Pin reported as an Output?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you will see the compilation report identifies the Direct‑to‑Factory Image pin as an output after completing a full compilation in Quartus® Prime Pro Edition Software targeting Agilex® 7 FPGA device and Agilex® 5 FPGA device. According to the Agilex® 7 FPGA Configuration User Guide and Device Configuration User Guide: Agilex® 5 FPGAs and SoCs, this pin is defined as an input. Resolution This is a reporting discrepancy found in the Quartus® Prime Pro Edition Software. The Direct‑to‑Factory Image pin is correctly defined as an input. This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.
What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.2?
Description The latest device firmware for Quartus® Prime Pro Edition Software version 24.2 is available for download below. Fixes for the following problems are included in the latest release (The newest release contains all prior fixes and supersedes earlier device firmware releases). Change Log Firmware version 0.04fw: This patch fixes the issue of incorrect data retrieval in the GET_I2C_TELEMETRY command. Firmware version 0.10fw: This patch fixes to reissue PLL lock request to achieve true independent PERST. Firmware version 0.54fw: This patch fixes issue where the HPS will get stuck at FSBL on certain units above Quartus 22.2B94 / or with firmware above 22.4B94. Firmware version 0.59fw: This patch includes fix to improves voltage sensor reading stability. Please also see the following links: Updating the SDM Firmware in the Agilex® 7 FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution Download the latest device firmware below. Note: Patches must be applied to the Quartus® Prime Pro Edition Software and the Quartus® Prime Pro Edition Software Programmer and Tools. Recompilation is not required. All programming files should be recreated. Re-run programming file generation or conversion using the Quartus® Prime Software programming file generator.What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3?
Description The latest device firmware for Quartus® Prime Pro Edition Software version 24.3 is available for download below. Fixes for the following problems are included in the latest release (The newest release contains all prior fixes and supersedes earlier device firmware releases). Change Log Firmware version 0.12fw: This patch fixes potential HBM2E calibration issues for Agilex® 7 FPGA M-Series devices. Firmware version 0.22fw: This patch fixes a rare scenario issue where the device hangs when reconfiguring back-to-back. The fix includes an update to the polling scheme in firmware to address the issue. Firmware version 0.25fw: This patch fixes an issue on Agilex® 7 FPGA devices where the HPS may become stuck at the First Stage Bootloader (FSBL). Firmware version 0.27fw: This patch fixes an issue where mailbox temperature inquiry would result in incorrect reading. It also fixes an issue where QSPI Write/Read would result in HW Ready error, an racing condition. Firmware version 0.34fw: This patch fixes a race condition in handling SHA isr and resumption of FPGA data blocks. Drain DMA post a configuration/PR to flush out left over data if any. Please also see the following links: Updating the SDM Firmware in the Agilex® 7 FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution Download the latest device firmware below. Note: Patches must be applied to the Quartus® Prime Pro Edition Software and the Quartus® Prime Pro Edition Software Programmer and Tools. Recompilation is not required. All programming files should be recreated. Re-run the programming file generation or conversion using the Quartus® Prime Software programming file generator.