Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteWarning(332174): Ignored filter at alt_sld_fab_0_st_dc_fifo_<unique ID>.sdc(Line number): *|in_wr_ptr_gray[*] could not be matched with a register
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see 'ignored filter' SDC warnings when your design includes the Partial Reconfiguration External Configuration Controller IP. Resolution This warning is safe to ignore and is scheduled to be removed in a future release of the Quartus® Prime Pro Edition Software. Related IP Core Partial Reconfiguration External Configuration Controller IPWhy does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system?
Description Due to a problem in the Ashling* RiscFree* IDE for Altera software version 25.2.1 (version dated 9 th May 2025), the Ashling* RiscFree* IDE might fail to detect other Nios ® V processor cores (except Core 0) for Nios ® V processor multicore designs. This is because there is a bug in the Ashling* GDBServer software. Error message: [GDB server output] Error: The device configuration selected has only 1 core (Core 0). Core 1 is not available. Resolution To workaround this issue, please switch from Ashling* GDBServer to Open On-Chip Debugger (OpenOCD) when debugging a Nios ® V multicore processor system. Add the “–o" argument when running niosv-download. niosv-download app.elf -o <options> This problem is scheduled to be fixed, beginning with the Ashling* RiscFree* IDE for Altera software version 25.3.1 (version dated 1 st August 2025).Why doesn’t Quartus® Prime Pro Edition Software version 25.3 generate programming files for my Agilex™ FPGA devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might not be able to generate programming files for some Agilex™ 5/3 FPGA devices. Here is the list of impacted OPNs: A5EG005BB18AE4S A5EG005BB18AE5S A5EG005BB18AE6S A5EG005BB18AE6X A5EG005BB18AI4S A5EG005BB18AI5S A5EG005BB18AI6S A5EG005BB18AI6X A5EG007BB18AE4S A5EG007BB18AE5S A5EG007BB18AE6S A5EG007BB18AE6X A5EG007BB18AI4S A5EG007BB18AI5S A5EG007BB18AI6S A5EG007BB18AI6X A3CZ025BB18AE7S A3CZ025BB18AI7S A3CZ050BB18AE7S A3CZ050BB18AI7S A3CZ065BB18AE7S A3CZ065BB18AI7S Resolution If you are using any of the listed devices in your design, download and install the patches below to enable programming file generation in Quartus® Prime Pro Edition Software version 25.3. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does Quartus® Prime Pro Edition Installer for software version 25.3 install an older version of Ashling* RiscFree* IDE for Altera® (version dated 31st Jan 2025)?
Description Due to a problem in the Quartus ® Prime Pro Edition Installer for software version 25.3, it installs an older version of Ashling* RiscFree* IDE for Altera ® software. For example: Quartus ® Prime Pro Edition software version 25.1 is paired with Ashling* RiscFree* IDE for Altera ® v25.1.1 (dated as 31 st Jan 2025). Quartus ® Prime Pro Edition software version 25.1.1 is paired with Ashling* RiscFree* IDE for Altera ® v25.2.1 (dated as 9 th May 2025). However, Quartus ® Prime Pro Edition software version 25.3 is paired with Ashling* RiscFree* IDE for Altera ® v25.1.1 (dated as 31 st Jan 2025). Thus, an older Ashling* RiscFree* IDE for Altera software is installed. This is because the installer is incorrectly packaged with the older software. Resolution To work around this problem in the Quartus ® Prime Pro Edition software version 25.3, please download the Ashling* RiscFree* IDE for Altera ® v25.2.1 (dated as 9 th May 2025) separately from the Quartus ® Prime Pro Edition Installer for software version 25.1.1. And use it with the Quartus ® Prime Pro Edition software version 25.3 for your project. You may follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select the appropriate Operating System. Download the Quartus® Prime Pro Edition Installer. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and ToolsWhy does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Why does Nios® V processor simulation fail when using the generated VHDL testbench from Platform Designer?
Description Due to a problem in the Quartus ® Prime Standard Edition software version 25.1, Nios ® V processor simulation may fail with the generated VHDL testbench system from Platform Designer for any processor design. This problem affects: All Altera ® FPGA device families in Quartus ® Prime Standard Edition software, and All Nios ® V processor variants (Nios ® V/g, Nios ® V/m, and Nios ® V/c processors). It is because the generation of the Nios ® V processor VHDL testbench system is not supported in Quartus ® Prime Standard Edition software version 25.1. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, please select “Verilog” at the “Create testbench simulation model” input option. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition software. Related Articles 3.3.1. Preparing Hardware Design for SimulationWhy does my PCIe* Independent GPIO PERST# test design fail to compile when I target the GXF_2ND_PERSTn signal on Pin CN11 of the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023)?
Description Due to a mistake on the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023), the PCIe* Independent GPIO PERST# is shown going to two Pin locations: GXF_2ND_PERSTn signal on Pin CN11 on Sheet 22 should be DNU (Do Not Use). GXF_1V2_2ND_PERSTn signal on Pin B46 on Sheet 16 is a valid GPIO on Bank 3A, and this should be used. Resolution When testing Independent GPIO PERST# in Bifurcated 2x8 Mode on the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023), either test in Single PERST# Mode when both x8 Cores are connected to the same host, or use Pin B46, which is a valid GPIO in Bank 3A. Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi-Channel DMA FPGA IP for PCI Express*
Why does the Agilex™3 FPGA and Agilex™ 5 FPGA Triple-Speed Ethernet IP Design Example, when configured with IEEE 1588v2, fail during simulation using Xcelium* and Riviera*-PRO simulators in Quartus® Prime Pro Edition Software version 25.1.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1, the Agilex™ 3 FPGA and Agilex™ 5 FPGA Triple-Speed Ethernet IP Design Example, when configured with IEEE 1588v2, may fail during simulation of the design example testbench. The following behaviors may be observed: Riviera*-PRO: Simulation may hang or display "Error: Accuracy criteria not met". Xcelium*: Simulation may pass, but accuracy criteria will not be met, leading to incorrect results. Resolution There is no workaround to this problem in the Quartus® Prime Pro Edition Software Version 25.1.1. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why is U-Boot not able to configure the Agilex™ 5 and Agilex™ 3 SDMMC controller in 8-bit bus width when booting from eMMC in releases 25.1.1 and before, regardless of bus-width = <8>; parameter is defined in the device tree?
Description Due to a silicon problem in Agilex™ 5 and Agilex™ 3 devices, the SRS16 capability register of the SDMMC controller incorrectly reports in the EDS8 bit (bit 18) that the controller does not support the eMMC 8-bit bus width mode. As a result, the U-Boot eMMC driver identifies 4-bit mode as the maximum supported width and configures the controller accordingly. This occurs even if the bus-width parameter is explicitly set to 8 in the device tree. Resolution To work around this problem, use the sdhci-caps and sdhci-caps-mask parameters in the U-Boot device tree to override the incorrectly reported values in the capability registers (SRS16 and SRS17). For this case, override bit 18 in SRS16 to indicate that an 8-bit bus width is supported. Example configuration: &mmc { status = "okay"; bus-width = <8>; sdhci-caps = <0x00000000 0x00040000>; sdhci-caps-mask = <0x00000000 0x00040000>; sd-uhs-sdr50; cap-mmc-highspeed; bootph-all; }; Verification in U-Boot: After applying the workaround, you can verify that the controller is using an 8-bit bus width by running the mmc info command: SOCFPGA_AGILEX5 # mmc info Device: mmc0@10808000 Manufacturer ID: 13 OEM: 4e Name: G1M15L Bus Speed: 52000000 Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 29.6 GiB Bus Width: 8-bit Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 29.6 GiB WRREL Boot Capacity: 31.5 MiB ENH RPMB Capacity: 4 MiB ENH Boot area 0 is not write protected Boot area 1 is not write protected This workaround will be permanently implemented in the Agilex™ 5/Agilex™ 3 U-Boot device tree in a future release of the FPGA HPS Embedded Software.
