Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.
Why is there a fitter failure when we are migrating x6 or x8 bonding design from 25.3 to 25.3.1?
Description Due to an improvement in Quartus® Prime Pro Edition software version 25.3.1, there is a change in the bonding placement for Agilex™ 5 GTS PMA/FEC Direct PHY IP. Following diagram shows the difference in the bonding placement between Agilex™ 5 GTS PMA/FEC Direct PHY IP in the Quartus Prime Pro Edition software version 25.3 and 25.3.1. Resolution For a workaround, for users that have designed their boards using the bonded port ordering in 25.3 or previous and do not want to change their physical pins or redesign, users can reassign their tx parallel data accordingly in RTL accordingly. Bank Mapping in 25.3 Current Mapping in 25.3.1 & Workaround for 25.3 x6 Bonding Bank 1C/4C CH3 tx_parallel_data [319:240] CH5 tx_parallel_data [479:400] --> Rearrange to tx_parallel_data [319:240] CH2 tx_parallel_data [239:160] CH4 tx_parallel_data [399:320] --> Rearrange to tx_parallel_data [239:160] CH1 tx_parallel_data [159:80] CH3 tx_parallel_data [319:240] --> Rearrange to tx_parallel_data [159:80] CH0 tx_parallel_data [79:0] CH2 tx_parallel_data [239:160] --> Rearrange to tx_parallel_data [79:0] Bank 1B/4B CH5 tx_parallel_data [479:400] CH1 tx_parallel_data [159:80] --> Rearrange to tx_parallel_data [479:400] CH4 tx_parallel_data [399:320] CH0 tx_parallel_data [79:0] --> Rearrange to tx_parallel_data [399:320] Mapping in 25.3 Current Mapping in 25.3.1 & Workaround for 25.3 x8 Bonding Bank 1B/4B CH3 tx_parallel_data [319:240] CH7 tx_parallel_data [639:560] --> Rearrange to tx_parallel_data [319:240] CH2 tx_parallel_data [239:160] CH6 tx_parallel_data [559:480] --> Rearrange to tx_parallel_data [239:160] CH1 tx_parallel_data [159:80] CH5 tx_parallel_data [479:400] --> Rearrange to tx_parallel_data [159:80] CH0 tx_parallel_data [79:0] CH4 tx_parallel_data [399:320] --> Rearrange to tx_parallel_data [79:0] Bank 1A/4A CH7 tx_parallel_data [639:560] CH3 tx_parallel_data [319:240] --> Rearrange to tx_parallel_data [639:560] CH6 tx_parallel_data [559:480] CH2 tx_parallel_data [239:160] --> Rearrange to tx_parallel_data [559:480] CH5 tx_parallel_data [479:400] CH1 tx_parallel_data [159:80] --> Rearrange to tx_parallel_data [479:400] CH4 tx_parallel_data [399:320] CH0 tx_parallel_data [79:0] --> Rearrange to tx_parallel_data [399:320]Why does the Synopsys VCS* simulator produce simulation errors with the F-Tile Ethernet Hard IP example design ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you may see the following simulation errors with the F-Tile Ethernet Hard IP example design. ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fd0, ReaddataValid = 1, Readdata = 01010142, Expected_Readdata = 00000000; ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fd4, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fd8, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fdc, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; The readdata values of these cwbin counter registers are expected values. The errors are due to wrong check tasks in testbench. Resolution Users can safely ignore these mismatching errors. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why are the peripherals under 2GB Peripheral Region still cached by the Nios® V/g processor?
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 23.1, 23.2, 23.3, 23.4, 24.1, 24.2, 24.3, 24.3.1, 25.1 Quartus® Prime Standard Edition Software version 23.1, 24.1 The Nios® V/g processor still caches the peripherals if they are placed under a Peripheral Region that is configured to 2GB, regardless of the Base Address. This is due to a problem in the processor RTL failing to correctly implement the 2GB Peripheral Region. Other Peripheral Region sizes are not affected; only 2GB is affected. Resolution To work around this problem, please select other Peripheral Region sizes except 2GB. The Nios® V/g processor still offers Peripheral Region sizes ranging from 64KB to 1GB. The 2GB Size option for Nios® V/g processor Peripheral Region is removed beginning with the Quartus® Prime Pro Edition Software version 25.1.1 and Quartus® Prime Standard Edition Software version 25.1. Related Article NIOS V/g - peripherals under 2GB Peripheral Region | Altera Community - 350829Why do I see an Quartus® Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16-bit PMA interface?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you will see a Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16 bit PMA interface and placed in 200G Hard IP. The Quartus Logic Generation Error message might be similar to one of the followings: Error(22144) Error(22658) Error(21843) Resolution There is no plan to fix this problem. To work around this error, you can take one of the below two methods: Change the clocking mode from PMA clocking mode to System PLL clocking mode, or Change the F-Tile placement from 200G Hard IP to 400G Hard IP.Why doesn’t the F-Tile Debug Toolkit in the F-Tile Avalon® Streaming IP for PCI Express* report error work in the Quartus® Prime Pro Edition Software v21.4 ?
Description Due to problems in the F-Tile Debug Toolkit in the Quartus® Prime Pro Edition Software v21.4, the F-Tile Debug Toolkit does not run when F-Tile is configured in 1 x4 endpoint mode. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. A patch is available to fix this problem for the Quartus Prime Pro Edition Software version 21.4. Download and install Patch 0.19 below. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 22.1.Why does the GTS JESD204B IP Design Example in Dual Simplex PHY only mode remain in the reset state when simulating with the VCSMX simulation tool?
Description Due to a problem in the 24.3.1 release of the Quartus® Prime Pro Edition software, the tx_out_of_reset output port is unconnected in the GTS JESD204B IP Design Example in Dual Simplex PHY only mode. This error causes the system to be unable to release both the link reset and frame reset. As the IP is in reset, the IP simulation fails to start. Resolution To work around this problem in version 24.3.1 of the Quartus® Prime Pro Edition software, connect u_jesd_gts_ed_qsys_RX_TX|jesd_gts_ss_rx_tx|ds_group_jesd204b|tx_phy_ds_group_0_inst0_auto_jesd204_tx_out_of_reset (export output port to top level) to wire named tx_out_of_reset[0] in top level wrapper (intel_jesd204b_gts_ed_RX_TX.sv) Additionally, Altera recommends installing the patch in the Quartus® Prime Pro Edition Software version 24.3.1. After installing the patch, regenerate the GTS JESD204B IP Design Example and run the simulation. This problem is fixed in version 25.1 of the Quartus® Prime Pro Edition Software.Why does the F-tile Serial Lite IV IP Design Example fail?
Description Due to a problem in the Clock Controller GUI of the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit, the F-tile Serial Lite IV IP Design Example fails when you need to configure the OUT1 clock frequency of the chip Si5332. This is because there is a problem with this Si5332 GUI; the OUT1 frequency can not be accurately configured. Similar failures might be seen for all Agilex™ 7 F-tile IP designs if you use the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit, your design utilizes the Si5332 OUT1 clock, and the default frequency, 166.66 MHz, needs to be changed. Resolution To work around this problem, you should avoid setting the Si5332 OUT1 frequency directly using the "set" button. You need to use the "import" button to accurately set the Si5332 OUT1 clock frequency. ClockBuilder Pro software can export the import function of a TXT file. A sample si5332 project and a si5332-project.txt file are attached for reference. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Why can't I download design examples in AN367?
Description Download the application note AN 367: Implementing PLL Reconfiguration in Stratix II Devices below. Page 31 mentions a design example #3 titled < Implementing Phase Shift Stepping Using the ALTPLL_RECONFIG Design with Write Parameters>. There is no link to this design example. Resolution You can download the design examples from this link: Design files for Application Note AN367. Related Articles AN 367: Implementing PLL Reconfiguration in Stratix II DevicesErrors: 'MODULAR_ADC_0_DUAL_ADC_MODE' undeclared here (not in a function)
Description Due to a problem with the Quartus® Prime Standard Edition Software version 21.1, when Modular ADC Core IP used in a Nios® II Gen 2 system, you might see the following errors when building the Nios® II software project: 'MODULAR_ADC_0_DUAL_ADC_MODE' undeclared here (not in a function) 'MODULAR_ADC_0_IRQ_INTERRUPT_CONTROLLER_ID' undeclared here (first use in this function) 'MODULAR_ADC_0_IRQ' undeclared here (first use in this function) 'MODULAR_ADC_0_NAME' undeclared here (not in a function) Resolution To work around this problem, the altera_modular_adc.h file located in \intelFPGA\21.1\ip\altera\altera_modular_adc\top\HAL\inc needs to be replaced with a new one. Download the driver.zip file to obtain the updated altera_modular_adc.h file. This problem is scheduled to be fixed in the Quartus® Prime Standard Edition Software version 22.1 and later versions.
