Why does the Synopsys VCS* simulator produce simulation errors with the F-Tile Ethernet Hard IP example design ?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you may see the following simulation errors with the F-Tile Ethernet Hard IP example design.

 ====>IP_INST[          0] Error!! MISMATCH! Read addr = 007fd0, ReaddataValid = 1, Readdata = 01010142, Expected_Readdata = 00000000; 

 ====>IP_INST[          0] Error!! MISMATCH! Read addr = 007fd4, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; 

 ====>IP_INST[          0] Error!! MISMATCH! Read addr = 007fd8, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; 

 ====>IP_INST[          0] Error!! MISMATCH! Read addr = 007fdc, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000;

The readdata values of these cwbin counter registers are expected values. The errors are due to wrong check tasks in testbench.

Resolution

Users can safely ignore these mismatching errors.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.