Is the Intel® Stratix® 10 timing model correct in the Intel® Quartus® Prime Pro Edition software versions 18.0 Update 1 and 18.1?
Description No, the Intel® Stratix® 10 timing model in the Intel® Quartus® Prime Pro Edition software version 18.0 Update 1 and 18.1 has a small miscorrelation. This is corrected in the Intel Quartus Prime Pro Edition software version 18.1 Update 1. These design scenarios may be affected: Designs that use source synchronous clocking Designs with transfers between the reference clock and the output clock for IOPLLs Designs with transfers between output clocks from different IOPLLs with different reference clocks Almost all designs will see timing delays change but most transfers will be unaffected because of either Common Clock Pessimism Removal (CCPR) or the transfer being asynchronous. Resolution All Intel Stratix 10 designs should be reanalyzed for timing in the Intel Quartus Prime Pro Edition software version 18.1 Update 1 or a patched version of 18.0 Update 1 or 18.1. Download and install Patch 1.45 for 18.0 Update 1 from the appropriate link below. Download the version 18.0 Update 1 patch 1.45 for Windows (.exe) Download the version 18.0 Update 1 patch 1.45 for Linux (.run) Download the Readme for the Intel Quartus Prime Pro edition software version 18.0 Update 1 patch 1.45 (.txt) Download and install Patch 0.31 for 18.1 from the appropriate link below. Download the version 18.1 patch 0.31 for Windows (.exe) Download the version 18.1 patch 0.31 for Linux (.run) Download the Readme for the Intel Quartus Prime Pro edition software version 18.1 patch 0.31 (.txt) For designs that are already in production: 1. Download and run the script lut8_iobuf_qsh_v3.tcl to check if the compiled design is affected by this problem. Command -> quartus_sh -t lut8_iobuf_qsh_v3.tcl -project <project name> -revision <revision name> -npaths 100 -debug 0 -verbose -check_lutmasks -vo_file simulation/modelsim/<revision name>.vo Output -> lut8check.rpt, iobuf.rpt, paths.csv iobuf.rpt and paths.csv report the paths that are affected by the timing model change 2. If there are no paths identified as impacted, no action is needed. 3. If there are paths identified as impacted and using the Intel Quartus Prime Pro Edition software version 18.1 or earlier, rerun timing analysis using the patched version of the Intel Quartus Prime Pro Edition software version 18.0 Update 1 or 18.1 a. If there is not sufficient margin then recompile the design. b. If there is sufficient margin, you may choose to perform no action Steps to rerun timing analysis: 1. Download and install patch 1.45 for 18.0.1 or patch 0.31 for 18.1 2. Open the design using the patched version of the Intel Quartus Prime Pro Edition software 3. Go to Tools -> Timing Analyzer and open Timing Analyzer. 4. Run the following commands: a. create_timing_netlist -model slow -force_dat b. read_sdc c. update_timing_netlist lut8check.rpt reports the LUTs impacted by the problem described in KDB Why do I have functional errors in my Intel® Stratix® 10 design? If this report contains "Found 0 LUTs with potentially incorrect bit settings" then the compiled design is safe. If the design is affected then the LUTs with this problem will be listed in the report.Why does the Intel® Quartus® Prime Standard Edition software fail to choose the 1.0V IO standard for Intel® MAX® 10 devices?
Description Due to a problem in the Intel® Quartus® Prime Standard Edition software version 20.1 and earlier, you may not be able to choose the 1.0V IO standard for 10M02/04/08/16 SAU324C8G Intel® MAX® 10 devices. Resolution To work around this problem, download and install the Intel® Quartus® Prime Standard Edition software version 20.1 patch 0.11 from the appropriate link below. After installing the patch, follow the steps provided in the readme files. Download patch quartus-20.1std-0.11std-windows.exe for Windows (.exe) Download patch quartus-20.1std-0.11std-linux.run for Linux (.run) Download the Readme for patch quartus-20.1std-0.11std-readme.txt (.txt)
Why is my IP license checked out and not released after using the Signal Tap Logic Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see that an IP license is checked out and not released when using the Signal Tap Logic Analyzer. Resolution To work around this problem, use the standalone version of the Signal Tap Logic Analyzer. This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition SoftwareError: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of space
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1, you might see this error when compiling your design in Design Space Explorer II. Error: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of space (Command was: lmap panel_name [::qed_lib::rdb_util::get_report_panel_names_matching -panel_name {} -string_match {Synthesis||Logic Synthesis Stage||Partition*||*Optimization Results||Multiplier Implementations||Multiplier Implementation Report} -regexp_match {}] {::qed_lib::rdb_util::get_report_panel_str -panel_name $panel_name})} Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.21 This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Why are HVIO pins not having the optional function SYSPLLREFCLK allowed to be assigned as a reference clock for the System PLL for the Agilex® 3 FPGA and Agilex® 5 FPGA GTS transceiver in the Quartus® Prime Pro Edition software version 25.1 and earlier?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1 and earlier, it incorrectly allows the assignment of other HVIO pins without the SYSPLLREFCLK description. An example of a correct selection would be the HVIO pin with the following optional functions listed: HVIO_5B_1, SYSPLLREFCLK_L1A_0, TXCLK1, Data_Ctrl1. This is the correct pin to select as a reference clock for the system PLL in the GTS transceiver bank 1A. An example of an incorrect selection would be an HVIO pin without the SYSPLLREFCLK optional function listing: HVIO_5B_20, TXCLK20, Data_Ctrl20. Therefore, selecting this as a reference clock pin for system PLL is incorrect, but the Quartus® Prime Pro Edition software does not currently report this as an error. Resolution To work around this problem, refer to the device pinout and pin connection guidelines and ensure it has the correct SYSPLLREFCLK optional function when selecting an HVIO pin as a system PLL reference clock. Agilex® 5 FPGA Device Pin-out Files Agilex® 5 FPGA Pin Connection Guidelines This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.Why does the Uncorrectable Error Count (ue_count) increase when a correctable error is injected in EMAC ECC and USB3.1 ECC?
Description Due to an EMAC and USB3.1 Tx and Rx ECC problem, when the user injects a correctable error into the EDAC Driver, it is observed that both the correctable error count (ce_count) and the uncorrectable counter (ue_count) are increased. The correct behavior should be that only the ce_count is increased and the ue_count remains unchanged. Resolution Currently there is no workaround. Additional Information The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3. (QPDS25.3_REL_GSRD_PR).Why do I intermittently see reboot failure in the u-boot stage when running the Arria® 10 GSRD from GitHub?
Description While doing repetitive reboots, occasionally the subsequent reboot will fail, and it will be stuck in the u-boot stage and can't be recovered. Error Message : U-Boot SPL 2025.01-gcd3a9044d661-dirty (Mar 27 2025 - 08:49:19 +0000) DDRCAL: Success DDRCAL: Scrubbing ECC RAM (1024 MiB). U-Boot SPL 2025.01-gcd3a9044d661-dirty (Mar 27 2025 - 08:49:19 +0000) U-Boot SPL 2025.01-gcd3a9044d661-dirty (Mar 27 2025 - 08:49:19 +0000) DDRCAL: Success DDRCAL: Scrubbing ECC RAM (1024 MiB). U-Boot SPL 2025.01-gcd3a9044d661-dirty (Mar 27 2025 - 08:49:19 +0000) Resolution Currently there is no workaround, users will need to power cycle the board to recover. Additional Information The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.1. (QPDS25.3.1_REL_GSRD_PR).Why does Quartus® Prime Pro compilation fail with error 23051 after upgrading the F-Tile HDMI IP Design Example to 25.1.1?
Description The F-Tile HDMI Altera® Design Example in Quartus® Prime Pro Edition Software 25.1.1 compilation fails at the Logic Generation stage, and Quartus® reports an error of the following form: Error(23051): NIOS data memory size 1024KBytes of Dynamic Reconfiguration Controller IP agx_hdmi21_frl_axi_demo/u_nios/dr_f/nios_dr_f is smaller than required MIF Size of 1141464Bytes to store the data in NIOS Memory This error also occurs after upgrading the F-Tile HDMI Altera® Design Example from previous versions. This is due to a significant memory increase in the MIF size required by the F-Tile Dynamic Reconfiguration (DR) IP. Resolution Increase the DR memory size in Quartus® Prime Pro Edition Software 25.1.1 to overcome the compilation error. A new memory size option is introduced in the Nios® data memory size within the Dynamic Reconfiguration IP GUI, which allows memory size selection up to 2048kB. i.e., double the maximum amount of memory previously. In the HDMI Design in Quartus, under Project Navigator, navigate to the IP Components tab and open nios_dr_f to launch the F-Tile Dynamic Reconfiguration Suite IP GUI. In the Dynamic Reconfiguration Controller IP tab ➤ Select NIOS data memory size option as 2048KBytes. Regenerate the DR IP by clicking on Generate HDL to regenerate the HDL files required. Recompile the design. #NOTE There will be an increase in M20K memory blocks in your chosen device when choosing this option Additional Information The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.Why is no display output observed when using the VVP-Full Design Example version 24.2 in the Arria® 10 FPGAs?
Description Due to problems porting the Nios® II Processor design to the Nios® V Processor design in the Quartus® Prime Pro Edition Software version 24.2, the Arria® 10 FPGA VVP-Full Design Example does not work correctly; no output is displayed. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.
