Why are there minimum pulse width timing violations in the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example?
Description High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP design examples, generated with Quartus® Prime Pro Edition 25.3 or prior, with the configuration settings described in tables 1 and 2, may present minimum pulse width timing violations. Parameter Value Choose the initiator to target the NoC mapping 16-to-16 crossbar connection Use Fabric NoC to return read responses via M20Ks Any Core clock frequency '> 500 MHz' for configurations with 'Use Fabric NoC to return read responses via M20Ks' set to 'Fabric NoC will not be used by the example design' '350 MHz' for all other 'Use Fabric NoC to return read responses via M20Ks' values NoC bridge hardware frequency '> 620 MHz' for configurations with 'Use Fabric NoC to return read responses via M20Ks' set to any value different from 'Fabric NoC will not be used by the example design' Table 1. High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example parametrization Reference Clock Signal Pin Assignment core_pll_refclk_clk Top HBM2E - PIN_AT41 (PLL: UIB_FBR_LEFT) - PIN_AP33 (PLL: UIB_FBR_RIGHT) Bottom HBM2E - PIN_EF29 (PLL: UIB_FBR_LEFT) - PIN_EH37 (PLL: UIB_FBR_RIGHT) Table 2. High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example pin assignment. The minimum pulse width timing violations are due to a combination of an oversized core_pll|core_pll|tennm_ph2_iopll-O_OUT_CLK2 (OUT_CLK) clock tree, the clock uncertainty from UIB PLLs, and the target frequency to drive core logic. An example minimum pulse width timing report showing the violations can be downloaded here. Resolution Resolution: To workaround the issue, select a different PLL to drive the example design core logic. Table 3 shows reference pins that connect to IOPLL not affected by this issue Reference Clock Pin IO Bank HBM2E Location PIN_N64 Bank 3A Top PIN_N52 Bank 3B Top PIN_G30 Bank 3C Top PIN_G18 Bank 3D Top PIN_FJ58 Bank 2A Bottom PIN_FH43 Bank 2B Bottom PIN_FR24 Bank 2C Bottom PIN_FJ6 Bank 2D Bottom As an alternative, you can adjust the core_pll|core_pll|tennm_ph2_iopll-O_OUT_CLK2 clock tree region to utilize only the clock sectors required to cover all the placed core logic in the chip. Refer to 6.6. Creating Clock Region Assignments in the Chip Planner section from the Quartus® Prime Pro Edition User Guide: Design Optimization for guidance on how to adjust the clock region. After adjusting the clock tree, your project QSF file will have a CLOCK_REGION assignment as follows: set_instance_assignment -name CLOCK_REGION "SX0 SY3 SX7 SY9" -to core_pll|core_pll|tennm_ph2_iopll~O_OUT_CLK2 -entity ed_synth This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.