Why do I unexpectedly observe intermittent DDM Errors?
Description Beginning January 10, 2026, executing commands in the terminal or GUI of Quartus® Prime Pro Edition software, Quartus Embedded Edition software or select standalone tools may cause the software or tool to crash with an error similar to the crash signature shown below. This error affects: Quartus Prime Pro Software versions v23.3 through v25.3.1 Standalone Quartus Prime Pro Programmer v23.3 through v25.3.1 Standalone Quartus Prime Pro Embedded Edition v25.3 and v25.3.1 Standalone Quartus Prime Pro Power Thermal Analyzer v25.3 through v25.3.1 This issue is not observed in Quartus Prime Pro Edition versions 23.2 or prior or Quartus Prime Standard Edition. Crash Signature: Error (22912): Unhandled exception: Fatal Error: Assertion failed tools/cpp/ddm/ddm_assessor.cpp:53: DDM_T::verify_token(token) : Cannot identify the client from function assertion_error in tools/cpp/ddm_report/ddm_report_msg.cpp@465 *** Fatal Error: Program termination requested *** *** Below is the stack trace at the time the error occurred. *** The lines beginning "Err Handler" represent frames relating *** to generating this report. *** The point at which the error occurred is somewhere after these lines. *** There may be a few frames representing standard/library code *** before the Quartus frames begin. *** The search for the error should begin with the Quartus frames. *** Unwinder: libunwind *** Stack depth: 15 Quartus 0x24e67: err_terminator() + 0x1bc (ccl_err) Quartus 0xb036a: __cxxabiv1::__terminate(void (*)()) + 0xa (stdc++) Quartus 0xb03d5: (stdc++) Quartus 0xb0628: (stdc++) Quartus 0x1680d: void ddm_throw<DDM_RUNTIME_ERROR>(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x26d (ddm_report) Quartus 0x13fae: DDM_REPORT::DDM_ASSERTION_HANDLER::assertion_error(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >) const + 0xde (ddm_report) Quartus 0x12a52: DDM_REPORT::ASSERTION_HANDLER::error(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >) + 0x72 (ddm_report) Quartus 0x13e64: DDM_REPORT::detail::assert_at_line(char const*, char const*, int, char const*, ...) + 0x1b4 (ddm_report) Quartus 0x205fb0: ddm_set_lassessor(DDM_T_ASSESSOR*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x60 (ddm) Quartus 0xf4445: DMS_MANAGER::DMS_MANAGER() + 0x5c5 (dni_dms) Quartus 0xf45b2: DMS_MANAGER::get() + 0x7a (dni_dms) Quartus 0xf6db4: _GLOBAL__sub_I_dms_manager.cpp + 0x58 (dni_dms) Quartus 0x647e: (ld-linux-x86-64) Quartus 0x6568: (ld-linux-x86-64) Quartus 0x202ca: (ld-linux-x86-64) Resolution To work around this problem: For Windows machines Download and unzip the Quartus Prime Pro version zip file that matches your Quartus Prime Pro version from this KDB. Double click on the executable ending in “windows.exe”. When the GUI pops up, press Next. Note that the GUI may look slightly different depending on the version of Quartus you are using. Accept the license agreement Specify the directory where the patch needs to be applied which may be a different location than Quartus install if you have standalone tools in a different directory from your Quartus Prime Pro software installation. Keep “Allow Patch to be uninstalled” selected. Select the software in which to install the patch: The patch will install in the directory of the software or tool you have selected. You will see an uninstall directory for the patch in your software or tool folder where patch is installed; it will contain an executable to uninstall the patch if required for any reason. To confirm patch is installed, you can run quartus_sh -v or corresponding version command for your tool via command line. Alternatively, you can Open Quartus in the GUI and select Help → About Quartus Prime in the main menu. If you are opening up a standalone tool you will navigate to Help-> About <tool_name>. For the Command Line Implementation of the patch in Windows, use the following command: <patch_filename.exe> --mode unattended --installdir <your_install_directory> --accept_eula 1 --patch_to [quartus|qprogrammer|qemb|pta] # An example to patch Quartus Prime Pro Edition Software v25.3: quartus-25.3-0.27-windows.exe --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 # An example to patch the Standalone Programmer for Quartus Prime Pro Software v25.3: quartus-25.3-0.27-windows.exe --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 --patch_to qprogrammer For Linux machines: Download and unzip the Quartus Prime Pro version zip file that matches your Quartus Prime Pro version from this KDB. Ensure you run chmod +x on the file ending with linux.run. Run in the command line: ./<installation_patch_run_file>. When GUI pops up, press Next. Note that the GUI may look slightly different depending on the version of Quartus you are using. Accept the license agreement Specify the directory where the patch needs to be applied which may be a different location than Quartus install if you have standalone tools in a different directory from your Quartus Prime Pro software installation. Keep “Allow Patch to be uninstalled” selected. Select the software in which to install the patch: The patch will install in the directory of the software or tool you have selected. You will see an uninstall directory for the patch in your software or tool folder where patch installed; it will contain an executable to uninstall the patch if required for any reason. To confirm patch is installed, you can run ./quartus_sh -v or corresponding version command for your tool via command line. Alternatively, you can Open Quartus in the GUI and select Help → About Quartus Prime in the main menu. If you are opening up a standalone tool you will navigate to Help-> About <tool_name>. For the Command Line Implementation of the patch in Linux, use the following command: ./<patch_filename.run> --mode unattended --installdir <your_install_directory> --accept_eula 1 --patch_to [quartus|qprogrammer|qemb|pta] # An example to patch Quartus Prime Pro Edition v25.3: ./quartus-25.3-0.27-linux.run --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 # An example to patch the Standalone Programmer for Quartus Prime Pro Software v25.3: ./quartus-25.3-0.27-linux.run --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 --patch_to qprogrammer This problem has been fixed in Quartus® Prime Pro Edition Software version 26.1. The below table lists the patches that are available and the associated patch number. The patch zip files are attached to the KDB below: Quartus Prime Pro Edition Version Patch Number 23.3 0.52 23.4 0.70 23.4.1 1.01 24.1 0.52 24.2 0.64 24.3 0.35 24.3.1 1.29 25.1 0.36 25.1.1 1.31 25.3 0.27 25.3.1 1.02
Why are there minimum pulse width timing violations in the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example?
Description High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP design examples, generated with Quartus® Prime Pro Edition 25.3 or prior, with the configuration settings described in tables 1 and 2, may present minimum pulse width timing violations. Parameter Value Choose the initiator to target the NoC mapping 16-to-16 crossbar connection Use Fabric NoC to return read responses via M20Ks Any Core clock frequency '> 500 MHz' for configurations with 'Use Fabric NoC to return read responses via M20Ks' set to 'Fabric NoC will not be used by the example design' '350 MHz' for all other 'Use Fabric NoC to return read responses via M20Ks' values NoC bridge hardware frequency '> 620 MHz' for configurations with 'Use Fabric NoC to return read responses via M20Ks' set to any value different from 'Fabric NoC will not be used by the example design' Table 1. High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example parametrization Reference Clock Signal Pin Assignment core_pll_refclk_clk Top HBM2E - PIN_AT41 (PLL: UIB_FBR_LEFT) - PIN_AP33 (PLL: UIB_FBR_RIGHT) Bottom HBM2E - PIN_EF29 (PLL: UIB_FBR_LEFT) - PIN_EH37 (PLL: UIB_FBR_RIGHT) Table 2. High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example pin assignment. The minimum pulse width timing violations are due to a combination of an oversized core_pll|core_pll|tennm_ph2_iopll-O_OUT_CLK2 (OUT_CLK) clock tree, the clock uncertainty from UIB PLLs, and the target frequency to drive core logic. An example minimum pulse width timing report showing the violations can be downloaded here. Resolution Resolution: To workaround the issue, select a different PLL to drive the example design core logic. Table 3 shows reference pins that connect to IOPLL not affected by this issue Reference Clock Pin IO Bank HBM2E Location PIN_N64 Bank 3A Top PIN_N52 Bank 3B Top PIN_G30 Bank 3C Top PIN_G18 Bank 3D Top PIN_FJ58 Bank 2A Bottom PIN_FH43 Bank 2B Bottom PIN_FR24 Bank 2C Bottom PIN_FJ6 Bank 2D Bottom As an alternative, you can adjust the core_pll|core_pll|tennm_ph2_iopll-O_OUT_CLK2 clock tree region to utilize only the clock sectors required to cover all the placed core logic in the chip. Refer to 6.6. Creating Clock Region Assignments in the Chip Planner section from the Quartus® Prime Pro Edition User Guide: Design Optimization for guidance on how to adjust the clock region. After adjusting the clock tree, your project QSF file will have a CLOCK_REGION assignment as follows: set_instance_assignment -name CLOCK_REGION "SX0 SY3 SX7 SY9" -to core_pll|core_pll|tennm_ph2_iopll~O_OUT_CLK2 -entity ed_synth This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does marginal degradation of 1.8V VIL I/O standard occur on Stratix® 10 FPGAs and Agilex™ FPGAs family SDM I/O pins after long-term operation?
Description On all Stratix® 10 FPGA and Agilex™ FPGA devices, when the board MSEL is set to JTAG but Quartus® Prime design software is configured to AS or AVST×8, and SDM I/O pins are left unconnected (NC), long-term operation may cause the 1.8V VIL on those SDM I/O pins to degrade below the datasheet specification of 0.5985V (0.35 × 1.71V). Refer to device datasheet under Single-Ended I/O Standards Specifications section for SDM IO I/O standard specification. The degradation can lead to configuration issues. Resolution Select AVST×16 as the configuration scheme in Quartus when using JTAG MSEL with all SDM I/O pins left unconnected. AVST×16 does not use any SDM I/O pins, preventing the degradation. Refer to Configuration User Guide for the steps to enable dual-purpose pins when setting AVSTx16 mode in Quartus. Starting in Quartus® Prime Pro edition software version 26.1, a note will be updated in the Configuration User Guide and the tooltips for the Configuration scheme category under Device and Pin Options in Quartus.Why does FPGA configuration (Phase 2) fail in HPS first boot mode on Agilex™ 5 and Agilex™ 3 SoC FPGAs when using Quartus® Prime Pro Edition Software version 25.3.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3.1, Phase 2 configuration (FPGA fabric configuration from HPS) may fail on Agilex™ 5 and Agilex™ 3FPGA devices when Phase 1 and Phase 2 bitstreams originate from different designs or design revisions. This is caused by HPS IO hash mismatches between compilations. Resolution To work around this problem, download and install the patch below. You must recompile both the design generating the Phase 1 bitstream and the design generating the Phase 2 bitstream using the patched version of Quartus® Prime Pro Edition Software version 25.3.1. Additional Information HPS IO hash mismatches can also occur for other reasons independent of this Quartus® Prime Pro Edition Software problem. For more information about other potential causes and how to avoid them, refer to the HPS IO Hash Compatibility section in the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCsWhy does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why doesn’t Quartus® Prime Pro Edition Software version 25.3 generate programming files for my Agilex™ FPGA devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might not be able to generate programming files for some Agilex™ 5/3 FPGA devices. Here is the list of impacted OPNs: A5EG005BB18AE4S A5EG005BB18AE5S A5EG005BB18AE6S A5EG005BB18AE6X A5EG005BB18AI4S A5EG005BB18AI5S A5EG005BB18AI6S A5EG005BB18AI6X A5EG007BB18AE4S A5EG007BB18AE5S A5EG007BB18AE6S A5EG007BB18AE6X A5EG007BB18AI4S A5EG007BB18AI5S A5EG007BB18AI6S A5EG007BB18AI6X A3CZ025BB18AE7S A3CZ025BB18AI7S A3CZ050BB18AE7S A3CZ050BB18AI7S A3CZ065BB18AE7S A3CZ065BB18AI7S Resolution If you are using any of the listed devices in your design, download and install the patches below to enable programming file generation in Quartus® Prime Pro Edition Software version 25.3. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Error: The dynamic chainout feature for fixed-point DSP is an advanced feature not supported in the current release. Disconnect the disable_chainout port and contact Altera for details.
Description This error message will be seen during compilation when using the Primitive DSP Native Fixed Point DSP Agilex™ FPGA IP and the "Enable disable_chainout" option is enabled. This problem only affects the Agilex™ 5 and Agilex™ 7 devices. Resolution To work around this problem, disconnect the disable_chainout port by setting parameter “Enable disable_chainout” to “No” in Native Fixed Point DSP Intel Agilex™ FPGA IP. Recompile on your design in the Quartus® Prime Pro Edition Software version 24.3 or later. Or, download and install patch for your Quartus® Prime Pro Edition Software version and recompile your design. Download and install Patch 0.00dsp for 23.1 from the appropriate link below: Download the version 23.1 patch 0.00dsp for Windows (.exe) Download the version 23.1 patch 0.00dsp for Linux (.run) Download the Readme for Patch 0.00dsp for Quartus® Prime Pro Edition Software version 23.1 (.txt) Download and install Patch 0.00dsp for 23.2 from the appropriate link below: Download the version 23.2 patch 0.00dsp for Windows (.exe) Download the version 23.2 patch 0.00dsp for Linux (.run) Download the Readme for Patch 0.00dsp for Quartus® Prime Pro Edition Software version 23.2 (.txt) Download and install Patch 0.00dsp for 23.3 from the appropriate link below: Download the version 23.3 patch 0.00dsp for Windows (.exe) Download the version 23.3 patch 0.00dsp for Linux (.run) Download the Readme for Patch 0.00dsp for Quartus® Prime Pro Edition Software version 23.3 (.txt) Download and install Patch 0.00dsp for 23.4 from the appropriate link below: Download the version 23.4 patch 0.00dsp for Windows (.exe) Download the version 23.4 patch 0.00dsp for Linux (.run) Download the Readme for Patch 0.00dsp for Quartus® Prime Pro Edition Software version 23.4 (.txt) Download and install Patch 0.00dsp for 24.1 from the appropriate link below: Download the version 24.1 patch 0.00dsp for Windows (.exe) Download the version 24.1 patch 0.00dsp for Linux (.run) Download the Readme for Patch 0.00dsp for Quartus® Prime Pro Edition Software version 24.1 (.txt) Download and install Patch 0.00dsp for 24.2 from the appropriate link below: Download the version 24.2 patch 0.00dsp for Windows (.exe) Download the version 24.2 patch 0.00dsp for Linux (.run) Download the Readme for Patch 0.00dsp for Quartus® Prime Pro Edition Software version 24.2 (.txt) For Agilex™ 7 and Agilex™ 5 design developed in Quartus® Prime Pro Edition Software prior to version 24.3, you may run the risk assessment script to check if your design is impacted. Steps to run the script: Run EDA Netlist Writer with the successfully pre-compiled design. Insert the risk assessment script in the Quartus project folder Navigate to the Quartus project folder: cd <quartus project path> Run the command: tclsh screening.tcl ./simulation/questa/<project_name>.vo Follow the message prompted for next step. For deployed designs with dynamic chainout enabled in the field, contact Altera by filing IPS case (stating bug ID 15017127180) for further queries.Does Agilex™ 3 support SmartVID optional functions for some pin names in the Quartus® Prime Pro Edition Software?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 for Agilex™ 3 FPGA devices, the Quartus® Prime Pro Edition Software incorrectly reports that SmartVID feature-related optional pin functions are available. The Agilex™ 3 FPGA devices do not support the SmartVID feature. The following pin functions are not available for the Agilex™ 3 FPGA devices: PWRMGT_SDA, PWGMGT_SCL, and PWRMGT_ALERT. Resolution For accurate pin information for the Agilex™ 3 FPGA devices, refer to the Agilex™ 3 FPGA Device Pin-Out Files, which are available from the Pin-Out Files for Altera® FPGAs. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why do several IP design examples fail on the Agilex™ 7 FPGA Series Transceiver SoC Development Kit?
Description The following IP Cores generate example designs for the Agilex™ 7 FPGA Series Transceiver SoC Development Kit with incorrect VID settings. 1) Serial Lite IV IP 2) Interlaken (2nd Generation) IP 3) Triple-Speed Ethernet IP 4) E-Tile Dynamic Reconfiguration IP 5) E-Tile Hard IP for Ethernet and CPRI PHY IP 6) JESD204B IP 7) JESD204C IP 8) Ethernet Subsystem IP Resolution The correct VID settings can be found in section 6.1, Add SmartVID settings in the Quartus® Prime QSF file of the Agilex™ F-Series Transceiver-SoC Development Kit User Guide. Update the design examples with the correct VID settings as shown below: set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 42 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 set_global_assignment -name USE_CONF_DONE SDM_IO16 set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13" set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.How do I remove the Altera JTAG Server service from my Windows computer?
Description To remove or delete the Altera JTAG Server service from your Windows computer, perform one of the sets of steps below: Uninstall the service using the Windows Command Prompt: Enter the following command at a Windows Command Prompt jtagserver --uninstall Reboot your computer Delete the service using the Windows Command Prompt: Enter the following command at a Windows Command Prompt sc delete Altera JTAG Server Reboot your computer If neither of the above options are acceptable, delete the service using the Windows Registry. It is recommended that you make a backup of the registry before making any changes to it. Open the Registry Editor by typing regedit at the Windows Command Prompt In the Registry Editor window, use the left-hand navigation pane to locate the folder HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Services\JTAGServer In the left-hand navigation pane, right-click on the JTAGServer folder and select Delete Reboot your computer
