Error(18957): Signal ~GND is constrained to be routed locally to port CLK0 on destination XXXX|auto_fab_0|alt_sld_fab_0|*|sld_signaltap_inst|*|altera_syncram_impl1|ram_block2a0, but this signal must be routed through global network
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.2 and later, you might see this error when compiling a Partial Reconfiguration (PR) design with Signal Tap targeting an Agilex™ 7 F/I-series FPGA device. Resolution To workaround this problem, follow these steps: Open the signal tap file. Navigate to Signal Configuration pane. Under RAM type selection, 3 options will be available (Auto, M20K and MLAB). Set the RAM type as MLAB as shown in the figure given below: Save the signal tap file and run the full compilation. Note: This restriction does not apply to Agilex™ 7 M-series production devices.
Why do the F2H (FPGA2HPS) subordinate signals showing "zzzzz"?
Description Due to a problem with the QuestaSim* SE on Quartus ® Prime Pro Edition Software version 25.1.1, when using the BFM testbench on F2H (FPGA2HPS) AXI4 and ACE-lite bridge, subordinate signals may appeared to have “zzz” or “ZZ” in the readings. Example of signal waveform in QuestaSim with “zzz” or “ZZ”: Impact: In QuestaSim, a "zzz" or "ZZ" signal usually indicates a high-impedance state (floating) or uninitialized value in the VHDL simulation, often appearing in the Wave window when signals are not being driven or have not received a value. Resolution Possible workarounds: Add Missing Pull-up/Pull-down resistors: If the signal is intended to be high or low when not driven, ensure a pull-up or pull-down resistor is properly modeled. Fix Unconnected Port: Ensure signal in the waveform is connected correctly in the testbench. Optimization Issues: Design optimization can cause signals to appear missing or in an incorrect state. Try adding +acc to the vsim command to improve visibility, e.g. vsim -voptargs=+acc <top_module> This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software.What Agilex® 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?
Description To meet the PCIe* spec requirement of 120 ms, the PCIe® REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz. Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only. Resolution This information has been scheduled for inclusion in the next release of the Agilex® PCI Express* IP User Guides. Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi Channel DMA FPGA IP for PCI Express* P-Tile Avalon® Streaming IP for PCI Express* R-Tile Avalon® Streaming IP for PCI Express* AXI Streaming IP for PCI Express* AXI Multichannel DMA IP for PCIe*Why are PCI Express RX TLP Packets lost when using the AXI Streaming IP for PCI Express* at lower rates (Gen1/2/3)?
Description Due to a problem in the 25.1 and earlier versions of the AXI Streaming IP for PCI Express*, RX TLP packets can be lost if the IP is generated for Gen5 data rates but is actually operating at lower rates, and back-to-back small RX TLPs are received where the TLPs appear in each segment. The R-Tile Avalon® Streaming IP for PCI Express* is not affected by this problem. Resolution No workaround to this problem exists in the 25.1 and earlier releases of the AXI Streaming IP for PCI Express*. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.Why does the F-Tile Ethernet Dynamic Reconfiguration (DR) design not work when one of the profiles has PTP enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 23.3, the F-Tile Ethernet designs using Dynamic Reconfiguration with PTP enabled on some of the profiles will fail to work correctly if the startup profile of the design does not have PTP enabled. Resolution To work around this problem, ensure that the startup profile of your dynamically reconfigurable Ethernet design has PTP enabled if any of the profiles have PTP enabled.Why does Quartus® Prime Pro Edition version 25.1.1 and later add a phased_clk_lock_interface conduit to the altera_eth_1588_tod IP when targeting Agilex® 7 FPGA devices?
Description In Quartus® Prime Pro Edition software version 25.1.1 and later, when targeting Agilex® 7 FPGA devices, the altera_eth_1588_tod IP exposes an additional phased_clk_lock_interface conduit. This interface conduit was not present in earlier Quartus® Prime Pro Edition versions. As a result, designs that were originally created and validated using Quartus® Prime Pro Edition version 25.1 or earlier may encounter connectivity issues or appear broken when migrated to newer software versions, due to the unexpected addition of this required conduit. Resolution To fix this problem in Quartus@ Prime Pro software version 25.3.1, install patch 1.23 below for the correct OS (Operating System) Readme: quartus-25.3.1-1.23-readme.txt Linux: quartus-25.3.1-1.23-linux.run Windows: quartus-25.3.1-1.23-windows.exe This problem is scheduled to be fixed in a future release of the Quartus@ Prime Pro Software.Which Protocols Support Spread Spectrum Clocking (SSC) in Agilex® 7 FPGA Devices?
Description In the Agilex® 7 FPGA device family, the Spread Spectrum Clocking (SSC) feature is supported only for specific protocol-based applications and can be optionally enabled for the following protocols: PCI Express (PCIe*) DisplayPort SATA/SAS (configured through the PMA/FEC Direct PHY IP) When using FGT transceivers in F-tile, SSC is enabled by selecting the “Enable Spread Spectrum Clocking” option, while keeping the “Enable TX FGT PLL fractional mode” option disabled in the F-Tile PMA/FEC Direct PHY IP. Resolution N/AWhy does Quartus® Prime Pro Edition report Critical Warning (22976) during the QTLG stage for F-Tile IPs not explicitly configured for Dynamic Reconfiguration when the F-Tile Dynamic Reconfiguration Suite IP is included in the same project?
Description In the Quartus® Prime Pro Edition software version 25.3.1, Critical Warning (22976) may be reported for non-Dynamic Reconfiguration F-Tile protocol IPs when they are instantiated in a design that also contains Dynamic Reconfiguration F-Tile IPs. This warning may appear even when Dynamic Reconfiguration is not required or intended for the non-DR F-Tile IPs. The warning message typically appears as follows: Critical Warning(22976): Dynamic Reconfiguration controller IP specification is missing for IP or IPs {IP_PATH}. Use IP_COLOCATE assignment to specify a Dynamic Reconfiguration controller IP. This warning does not affect design functionality or correctness. It is reported due to how Quartus® Prime Pro Edition software checks for Dynamic Reconfiguration controller assignments when both Dynamic Reconfiguration and non-Dynamic Reconfiguration F-Tile IPs are present in the same design. Resolution There is currently no workaround to suppress Critical Warning(22976) in the Quartus Prime Pro Edition software. If Dynamic Reconfiguration is not required for the IP reporting this warning, this warning can be safely ignored. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Error: Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see this error message during the Support-Logic Generation stage when compiling a design on the Windows* Operating System. This error occurs when Windows* long path support is disabled. Windows* limits the combined length of a file name and its path to 260 characters. If the project path exceeds this limit, the Quartus® Software cannot access required IP or design files. Resolution To work around this problem, enable Windows* long path support by updating the registry: a) Open Registry Editor: Press Windows Key + R, type regedit, and press Enter. b) Navigate to HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem c) Find LongPathsEnabled. Double-click it and set "Value data" to 1. If the LongPathsEnabled doesn't exist, right-click, select New > DWORD (32-bit) Value, and name it LongPathsEnabled. d) Restart your computer. This error message will be enhanced in a future release of the Quartus ® Prime Pro Edition Software.Warning(332158): Clock uncertainty characteristics of the Agilex™ 7 FPGA device family are preliminary
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and earlier, you may encounter this warning message during the Fitter stage when compiling designs targeting Agilex™ 7 FPGA devices. Although the release notes indicate the timing model is final, the warning message may still appear. Resolution After reviewing the release notes, confirming that the timing model for the Agilex™ 7 FPGA devices is final, you can safely disregard this warning message. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3. Additional Information Quartus® Prime Pro Edition: Version 25.1 Software and Device Support Release Notes
