Warning(332174): Ignored filter at alt_sld_fab_0_st_dc_fifo_<unique ID>.sdc(Line number): *|in_wr_ptr_gray[*] could not be matched with a register
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see 'ignored filter' SDC warnings when your design includes the Partial Reconfiguration External Configuration Controller IP. Resolution This warning is safe to ignore and is scheduled to be removed in a future release of the Quartus® Prime Pro Edition Software. Related IP Core Partial Reconfiguration External Configuration Controller IPWhy does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system?
Description Due to a problem in the Ashling* RiscFree* IDE for Altera software version 25.2.1 (version dated 9 th May 2025), the Ashling* RiscFree* IDE might fail to detect other Nios ® V processor cores (except Core 0) for Nios ® V processor multicore designs. This is because there is a bug in the Ashling* GDBServer software. Error message: [GDB server output] Error: The device configuration selected has only 1 core (Core 0). Core 1 is not available. Resolution To workaround this issue, please switch from Ashling* GDBServer to Open On-Chip Debugger (OpenOCD) when debugging a Nios ® V multicore processor system. Add the “–o" argument when running niosv-download. niosv-download app.elf -o <options> This problem is scheduled to be fixed, beginning with the Ashling* RiscFree* IDE for Altera software version 25.3.1 (version dated 1 st August 2025).Why does Quartus® Prime Pro Edition Installer for software version 25.3 install an older version of Ashling* RiscFree* IDE for Altera® (version dated 31st Jan 2025)?
Description Due to a problem in the Quartus ® Prime Pro Edition Installer for software version 25.3, it installs an older version of Ashling* RiscFree* IDE for Altera ® software. For example: Quartus ® Prime Pro Edition software version 25.1 is paired with Ashling* RiscFree* IDE for Altera ® v25.1.1 (dated as 31 st Jan 2025). Quartus ® Prime Pro Edition software version 25.1.1 is paired with Ashling* RiscFree* IDE for Altera ® v25.2.1 (dated as 9 th May 2025). However, Quartus ® Prime Pro Edition software version 25.3 is paired with Ashling* RiscFree* IDE for Altera ® v25.1.1 (dated as 31 st Jan 2025). Thus, an older Ashling* RiscFree* IDE for Altera software is installed. This is because the installer is incorrectly packaged with the older software. Resolution To work around this problem in the Quartus ® Prime Pro Edition software version 25.3, please download the Ashling* RiscFree* IDE for Altera ® v25.2.1 (dated as 9 th May 2025) separately from the Quartus ® Prime Pro Edition Installer for software version 25.1.1. And use it with the Quartus ® Prime Pro Edition software version 25.3 for your project. You may follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select the appropriate Operating System. Download the Quartus® Prime Pro Edition Installer. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and ToolsWhy does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Why does my PCIe* Independent GPIO PERST# test design fail to compile when I target the GXF_2ND_PERSTn signal on Pin CN11 of the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023)?
Description Due to a mistake on the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023), the PCIe* Independent GPIO PERST# is shown going to two Pin locations: GXF_2ND_PERSTn signal on Pin CN11 on Sheet 22 should be DNU (Do Not Use). GXF_1V2_2ND_PERSTn signal on Pin B46 on Sheet 16 is a valid GPIO on Bank 3A, and this should be used. Resolution When testing Independent GPIO PERST# in Bifurcated 2x8 Mode on the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023), either test in Single PERST# Mode when both x8 Cores are connected to the same host, or use Pin B46, which is a valid GPIO in Bank 3A. Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi-Channel DMA FPGA IP for PCI Express*
How accurate are the CDR Function Pins in the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA Pinout Files?
Description Due to a problem in the pinout files and the Quartus® Prime Pro Edition Software version 25.1 and prior for the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA, the CDR function pin assignments in the bottom index sub-bank are incorrectly documented. Specifically: Pins with index 10/11, 22/23, 34/35, and 46/47 are mistakenly listed as supporting the CDR function. Conversely, pins with index 0/1, 12/13, 24/25, and 36/37, which do support the CDR function, are incorrectly marked as not supporting it. Resolution To work around this issue, users should update their board designs by reassigning the CDR function from the incorrect pin index to the correct ones as follows: Incorrect Pin Index Correct Pin Index 10/11 0/1 22/23 12/13 34/35 24/25 46/47 36/37 Designers are advised to validate pin assignments using the LVDS SERDES IP in Quartus® Prime Pro Edition Software rather than relying solely on the pinout files or Pin Planner. This problem is scheduled to be fixed in the pinout files and in a future release of Quartus® Prime Pro Edition Software.Why are there functional failures after partial reconfiguration in Agilex™ 7/5/3 FPGA designs?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 23.2 to 25.1, you might have functional failures after partial reconfiguration (PR) in some Agilex™ FPGA devices. The failure has FPGA unit and design dependencies and does not occur in all devices. It is a time zero failure for the affected FPGA units. The problem affects all Agilex™ FPGA portfolio devices. Resolution To work around this problem: Convert your base SOF to RBF/JIC/RPD* (Base bitstream for full-chip configuration) and PR PMSF to RBF (PR bitstream) using the Quartus® Programming File Generator v25.1.1. Use the Quartus® Programmer v25.1.1 to program the Base and PR bitstreams. The problem is fixed starting with the Quartus® Prime Pro Edition Software version 25.1.1. *RPD file format is for third party programming methods, not supported in Quartus® Prime Programmer.How to run Agilex™ Multiple EMIF Designer Tool in Agilex™ 7 FPGA and SoC FPGA M-Series, Agilex™ 5 FPGA and SoC FPGA, and Agilex™ 3 FPGA and SoC FPGA?
Description You can merge multiple EMIF design examples by configuring the required interconnections using Quartus® Prime Platform Designer. This manual process involves setting up and verifying each connection to ensure proper integration. Resolution To streamline and automate the merging of multiple EMIF designs, use the Agilex™ Multiple EMIF Designer Tool (AMED). This tool simplifies the integration process by handling the configuration steps automatically, reducing the potential for errors and saving time. You can download the AMED tool below. Follow the steps below to utilize the AMED tool: Copy all the *.tcl files into the same directory. Open a terminal: On Windows*, open Command Prompt. On Linux*, open Konsole or your preferred terminal. Navigate to the directory containing the *.tcl files using the cd command. Run the script by entering the command: tclsh multi_emif.tcl Navigating the AMED GUI: Select the number of designs to merge. Browse and add each design’s directory path. Set the output directory for the merged design. (Optional) Check Run Analysis & Synthesis to complete this stage automatically. Click Generate to start merging. Additional Information Note: Ensure that you specify the installation paths for standalone Quartus® environments as applicable: For Windows* standalone installation, provide the path, for example: C:/altera_pro/25.1/quartus For Linux* standalone installation, specify the appropriate installation directory path up to the “quartus” folder (e.g., /path/to/quartus). This step is not required when using Network-Based Quartus® installations on Linux*.Why do I see a large timing violation when using the IOPLL IP’s Non-Dedicated Feedback Path option?
Description A timing violation may occur when the Non-Dedicated Feedback Path option is enabled in the IOPLL IP. This is caused by the C-counter starting to toggle unexpectedly, resulting in a phase shift of the output clocks relative to the input clock. This problem affects the following device families: Stratix® 10 FPGAs Agilex™ 3 FPGAs Agilex™ 5 FPGAs Agilex™ 7 FPGAs Resolution To address this timing violation, add multi-cycle constraints to the impacted timing paths. 1) The set_multicycle_path constraint should only be applied to the affected path. 2) The affected clock domain can be either the source or the destination clock domain in the timing transfers that this behavior may impact.Why True Differential input buffer with on-chip differential Termination (RD OCT) enabled does not respond after device is configured for Agilex™ 3 FPGA, Agilex™ 5 FPGA, and Agilex™ 7 FPGA devices?
Description The on-chip differential termination (RD OCT) for the True Differential input buffer is not enabled correctly in Quartus® Prime software. This issue impacts all True Differential Signaling (TDS) input buffer with RD OCT enabled, except when such input standard is used as the EMIF interface reference clock. Resolution This issue will be fixed progressively according to devices in the Quartus® Prime software. Refer to the tables below for the fix plan per device and Quartus® Prime version. Part Number Quartus® Prime v25.1 Quartus® Prime v25.1.1 Quartus® Prime v25.3 AGMxxxxxxxxxxVR0 Not Fixed Not Fixed Fixed AGMxxxxxxxxxxxVC Not Fixed Fixed Fixed A5Ex013xxxxxxxSR0 Not Fixed Not Fixed Fixed A5Ex013xxxxxxxS/V/XCS/R1 A5Ex008xxxxxxxS/V/XCS/R1 Not Fixed Fixed Fixed A5Ex065xxxxxxxSR0 Not Fixed Not Fixed Fixed A5Ex065xxxxxxxS/V/E/X A5Ex052xxxxxxxS/V/E/X A5Ex043xxxxxxxS/V/E/X Not Fixed Not Fixed Fixed A3CxxxxxxxxxxxS Not Fixed Fixed Fixed Alternatively, you may use the below .tcl script to fix the differential termination settings in your .sof file manually. Please contact Altera Support team for assistance.
