CONSTRA error: Failed to open file 'C:\altera_pro\26.1\devices/10nm/sm7revb/hviowr_pllwrap_bf_rbc_constraints.ddb'

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see the following or similar simulation error message when simulating a design targeting an Agilex® 7 FPGA M-Series device or an Agilex® 3 FPGA C-Series device:

CONSTRA (ed_sim.phylite_ph2_0_example_design.phylite_ph2_0_example_design.core.arch_inst.phylite_clocking_inst.iopll_inst.tennm_ph2_iopll_encrypted_inst): error: Failed to open file 'C:\altera_pro\26.1\devices/10nm/sm7revb/hviowr_pllwrap_bf_rbc_constraints.ddb'

This CONSTRA error occurs because the SystemVerilog Constraint Solver executable file cannot find simulation files due to missing directories from the Quartus installation path, under the directory <Quartus_version>/devices/10nm. The missing directories are part of the Agilex® 5 FPGA device support files.

Resolution

To work around this problem:

1. Download the Agilex® 5 FPGA device support file, according to the Quartus® Prime Pro Edition Software version and operating system.
2. Install the downloaded Agilex® 5 FPGA device support file.
3. Simulate your design again using a fresh simulation directory.

This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.