Why does U-Boot initially read incorrect information from the EMIF controller Read-Only registers, but later retrieve the correct information on Agilex® 3, Agilex® 5, and Agilex® 7 FPGA M-Series devices in Quartus® Prime Pro edition software 26.1.1 and earlier?
Description Due to a synchronization issue between U-Boot and the IOSSM firmware, U-Boot may read incorrect values from EMIF controller read-only registers, such as MAILBOX_HEADER and MEM_TOTAL_CAPACITY_INTF. This occurs when U-Boot accesses these registers before the IOSSM firmware has completed their initialization. Once the IOSSM firmware initializes the registers, subsequent reads return the correct values. This issue is observed in Agilex® 3, Agilex® 5, and Agilex® 7 FPGA M-Series devices when using Quartus® Prime Pro Edition Software version 26.1.1 and earlier releases. Resolution A permanent fix is planned for a future release and will include the following enhancements: The IOSSM firmware will set the MB_READY bit (bit 31) in the MAILBOX_HEADER register of the EMIF Controller to 1, indicating that the read-only registers have been fully initialized. U-Boot will poll the MB_READY bit in the MAILBOX_HEADER register and wait for it to be asserted before reading any other read-only registers in the EMIF Controller. This behavior will be enabled only when the CONFIG_IO96B_MB_READY Kconfig option is selected. To maintain compatibility with earlier IOSSM firmware versions that do not support the MB_READY bit, the CONFIG_IO96B_MB_READY option will be disabled by default.Why Do I Receive the Critical Warning IPC-40026: System Clock Frequency Mismatch in a GTS SDI II Design with Dynamic Reconfiguration?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1.1, a critical warning may be displayed when using the GTS SDI II Design Example. This warning occurs because the SysPLL parameter is configured with the GTS PMA/FEC Direct PHY IP (TX/RX Simplex) settings instead of the GTS PMA/FEC Direct PHY IP (Dynamic Reconfiguration) settings. Resolution This warning can be safely ignored, as it does not affect the functionality or operation of the design. This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why do I see this warning message after enabled Transceiver Toolkit Debugging Features in Serial Design ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, you will observe below. “warning check failed! > warning: no path is found satisfying assignment" “set_max_skew -from get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|in_wr_ptr_gray -to get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|write_crosser|sync.u|din_s1 -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 - This assignment will be ignored.” It happen when enabled Transceiver Toolkit Debugging Features in Serial Design. This problem happens due to undefined the path of the dc_fifo.sdc. Resolution This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why am I seeing High Severity DA warning Multiple Clock Domains Driving a Synchronizer Chain after I enabled Transceiver Toolkit Debugging Features in Dual-Simplex Parallel loopback with external and without VCXO Design Example ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1 you may see there is different clock domains driven in a synchronizer chain causing high severity DA warning in report compilation Resolution This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why is the maximum number of I/O PLLs incorrectly reported in the Total PLLs Fitter Summary report?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and earlier, you might see that the maximum number of I/O PLLs for Agilex® 5 FPGA devices is stated incorrectly in the Total PLLs Fitter Summary report. Resolution The compilation will pass as long as the number of I/O PLLs used in the design does not exceed the actual maximum number of I/O PLLs supported by the specific device. The correct maximum number of I/O PLLs supported can be checked from the PDF with the title of Agilex 5 FPGAs and SoCs <Series> Product Table. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.Why is there "sopcinfo2swinfo.exe: command not found" when running sopc-create-header-files under WSL, or Docker under Windows?
Description An error message like this: sopc-create-header-files: line 182: sopcinfo2swinfo.exe: command not found sopc-create-header-files: sopcinfo2swinfo.exe --input=./peripheral_subsys.sopcinfo --output=/tmp/sopc-create-header-files.1312.tmp.swinfo failed will be seen in the Quartus ® Prime Pro Edition Software version 25.3.1 and earlier, when using the sopc-create-header-files script within the Linux version of the Quartus ® Prime Pro Edition Software, running on the Microsoft* Windows operating system. The Linux version of the tools can be installed under Windows* using WSL, WSL2 or Docker. In all of these cases, the sopc-create-header-files script detects that it is running under Windows* and looks for an internal tool with the suffix “.exe”. However, since the Linux version has been installed, the tool does not have that suffix and so cannot be found by the sopc-create-header-files script. Resolution To work around the problem, either switch to using a Windows* installation of the Quartus® Prime Pro Edition Software, or follow these steps to continue using the Linux installation under Windows*: Under Linux, use the command “which sopc-create-header-files” to find the location of the script. Copy the script from this location to another location of your choice. Make the newly copied script version writable using the command: chmod +w <path to newly copied script> Modify your newly copied script version. Find the following line: windows_exe=.exe and either remove it or add a single # symbol at the start to comment it Use your newly modified version of the script instead of the installed version. This will now execute correctly.Why there is Missing location assignment warnings on hps_io interfaces (SDMMC, UART, I3C) in Quartus® Prime Pro Edition Software version 25.1.1 and earlier?
Description Due to a problem in Quartus® Prime Pro Edition Software v25.1.1 and earlier. You might see the warnings messages “Missing location assignment” on some of the hps_io interfaces due to the mismatch interface name. Resolution This problem is resolved in Quartus® Prime Pro Edition Software v25.3.Why does GD55LB02GE QSPI flash fail in Linux* in FPGA SoC device?
Description If you use Linux* version between socfpga-6.0 and socfpga-6.12.43-lts with GD55LB02GE QSPI flash, you may fail to mount the file system in Linux if it’s stored in GD55LB02GE. This is caused by the gigadevice.c in these versions. Resolution This issue is fixed in socfpga-6.12.43-lts and afterwards. You can upgrade Linux source code to this version, or comment out the GD55LB02GE entry in gigadevice.c in old versions.Why is the HPS Xen Hypervisor GSRD for the Agilex™ 5 FPGA E-Series Premium Dev Kit not supported in release 25.3.1?
Description Due to the gradual GSRD migration from legacy (GSRD 1.0) to Baseline (GSRD 2.0) for the Agilex™ 5 FPGA E-Series Premium Dev Kit, the Legacy GSRD to boot from SD Card was deprecated in release 25.3.1. Since the Xen GSRD still makes use of Legacy GSRD, this is not supported in this release. Resolution There is not a workaround for this problem, but you can still use the latest Xen GSRD available from release 25.3: HPS Xen Hypervisor GSRD for the Agilex™ 5 FPGA E-Series Premium Dev Kit. This problem will be fixed in a future release once the Xen GSRD gets ported to use the Baseline GSRD. Additional InformationCannot enable SPIM0 and SPIS0 routing to FPGA at the same time. Disable one of these in Advance FPGA Placement
Description The Quartus Prime software does not allow the routing of both the SPI master (SPIM) and SPI slave (SPIS) interfaces to the FPGA fabric simultaneously for the same SPI instance. This restriction applies to SPIM0/SPIS0 and SPIM1/SPIS1. Resolution When configuring SPI routing to the FPGA, enable either the master or the slave interface for each SPI instance, but not both at the same time. For example: SPIM0 and SPIS0 cannot be enabled together SPIM1 and SPIS1 cannot be enabled together
