Why do Agilex® 5 FPGAs and Agilex® 3 FPGAs SEU report incorrect bits position within the frame and/or combination of row and frame index in the Quartus® Prime Pro Edition 25.1?
Description The total frame range for the Agilex® 5 FPGA and the Agilex® 3 FPGA devices is from bit0-bit12 (total 13 bits), while the maximum frame covered in the current Advanced SEU Detection IP, ASD IP, is from bit0-11(total 12 bits). The ASD IP frame range(12 bits) does not cover all the row and frame index combinations for the Agilex® 5 FPGA and the Agilex® 3 FPGA devices. This issue is also affecting the Fault Injection Debugger Tool, FID tool. As a result, the ASD IP and FID tool might report the incorrect bit position within the frame and/or the combination of row and frame index. Besides, you might not get an error when you read the Error Message Queue, although you have successfully injected the SEU error. You cannot insert SEU in the frame range between 1000- 1FFF. Instead, SEU error will be inserted in the frame range from 0- FFF. However, the SEU detection and correction are still fine for the entire bit and frame. Resolution To inject the SEU error to a pre-defined safe location: insert a safe SEU error with the mailbox command (INSERT_SAFE_SEU_ERROR 0x41) or the FID tool. Then, read the SEU with mailbox command (READ_SEU_ERROR 0x3C) or read the avst_seu_source_data signal of the ASD IP. Refer to the SEU Error Message Queue Bit Description in the SEU Mitigation User Guide: Agilex® 5 FPGAs and SoCs and Agilex® 3 FPGAs and SoCs to decode it. Note: Do not use READ_SEU_ERROR 0x3C mailbox command if your design contains the Advanced SEU Detection IP. Request a patch to inject into another location not listed in the pre-defined safe location. This is scheduled to be fixed in a future release of Quartus® Prime Pro Edition Software.
Why are there intermittent calibration failures in the External Memory Interfaces Agilex® 5 FPGA E-Series IP?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you may run into intermittent EMIF calibration failures on LPDDR4 1CHx32, 2-Rank configurations running at 1333 MHz on Agilex® 5 FPGA E Series devices. Resolution To work around this problem, disable cross-rank delay averaging by enabling the following debug flag in the parameter table: DBG_CFG_DISABLE_RANK_AVG_AND_OVR This prevents the firmware from averaging DQS-WR delays across ranks, which eliminates the invalid delay setting that causes the MGN-stage calibration failure. Note: Disabling rank averaging may affect traffic stability in some configurations. A patch is available to fix this problem in Quartus Prime Pro Edition Software version 25.3.1. Download and install the below 1.04 patch. This problem has been fixed beginning with version 26.1 of the Quartus Prime Pro Edition Software.
drivers/src/altera_s10_mailbox_client.c:32:59: error: 'OS_FLAG_SET' undeclared (first use in this function); did you mean 'ALT_FLAG_SET'?
Description Due to a problem in Quartus® Prime Pro Edition Software, you might see an error when compiling Nios® V software with the Mailbox Client IP or 16550 Compatible UART Core driver, in FreeRTOS environment. This is because the driver software of the IP is using “MicroC/OS-II”-specific OS_* macros. Resolution The recommended macros are the OS-independent ALT_* macros. MicroC/OS-II Real-Time Operating System - Thread-Safe HAL Drivers FreeRTOS Real-Time Operating System - Thread-Safe HAL Drivers Replace the OS_* accordingly. MicroC/OS-II Macros Replace to OS_FLAG_SET ALT_FLAG_SET OS_FLAG_CLEAR ALT_FLAG_CLEAR OS_FLAG_WAIT_SET_ALL ALT_FLAG_WAIT_SET_ALL_WO_CONSUME (OS_FLAG_WAIT_SET_ALL + OS_FLAG_CONSUME) ALT_FLAG_WAIT_SET_ALL_WITH_CONSUME OS_FLAG_WAIT_SET_ANY ALT_FLAG_WAIT_SET_ANY_WO_CONSUME (OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME) ALT_FLAG_WAIT_SET_ANY_WITH_CONSUME OS_FLAG_GRP* group ALT_FLAG_GRP(group)Why are Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach missing from Quartus® Prime Pro software IP Catalog?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 and 26.1, Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach are missing from IP Catalog. It is due to a bug in the IP Catalog. Refer to Embedded Peripherals IP User Guide - Device Support (PDF) for the Vectored Interrupt Controller IP device support. Refer to Nios® II – Lauterbach Trace32 Debug system for more information about Trace Interface IP for Lauterbach. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 26.1. Download and install patch 0.11 below. Quartus® Prime Pro Edition Software v26.1 Patch 0.11 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does Board Support Package (BSP) Editor in Quartus® Prime Pro Embedded Edition fails to generate Nios® V processor BSP project from .vds file?
Description Due to a problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, the BSP Editor fails to generate Nios® V processor BSP project from .vds file. This issue is not affecting BSP project generation: From .qsys file using BSP Editor in Quartus® Prime Pro Embedded Edition software, or Using BSP Editor in Quartus® Prime Pro Edition software. This issue is caused by a software bug in the BSP Editor of Quartus® Prime Pro Embedded Edition software. Refer to Nios V Embedded Processor Design Handbook - Recommended Tools from Quartus Prime Installer (PDF) for more information on the difference between Quartus® Prime Pro Edition and Quartus® Prime Pro Embedded Edition software. Resolution To work around this problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, apply either one of the workarounds below: Switch from .vds to .qsys file Use BSP Editor in Quartus® Prime Pro Edition software version 26.1 or 26.1.1 This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Embedded Edition Software.Why does simulation of example design using GTS Dynamic Reconfiguration Controller fail with Riviera* simulator but pass with all other simulators?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, you may see simulation of example designs using GTS Dynamic Reconfiguration Controller IP fails using Riviera simulator but passes with all other simulators. This is because simulation-specific behavior in the Riviera simulator causes failure. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why am I seeing simulation failure for GTS Dynamical Reconfiguration Controller IP designs when using Cadence* Xcelium* simulator?
Description Due to a problem in the Cadence* Xcelium* simulator version 24.09.004, you may see simulation failure for GTS Dynamic Reconfiguration Controller IP designs. This problem is seen in the Quartus® Prime Pro Edition software version 25.1.1. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 25.1.1, you need to use Cadence Xcelium simulator version xcelium 23.09.004. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why is the external loopback test failing for the GTS Dynamic Reconfiguration Controller IP in the GTS PMA/FEC Direct PHY example design?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and 25.3, you may notice that the external loopback test is not working correctly for the GTS Dynamic Reconfiguration Controller IP for the GTS PMA/FEC Direct PHY example design. This is due to incorrect settings in the hardware tcl scripts inside the “hwtest” folder. You may notice the external loopback test shows “DR Test Passed” in the system console; however, it does not change the DR profile for GTS PMA/FEC Direct PHY IP. Resolution As a workaround, modify the tcl script file as shown below: Go to “hardware_test_design/hwtest” folder: Replace the “dr_ctrl_csr_reg_map.tcl ” file inside the “hwtest/src” folder with the attached file. Replace the “dr_dphy_test.tcl” file inside the “hwtest/tests” folder with the attached file (hwtest.zip). This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.1.Why can't I find an update to the GTS Transceiver Dual Simplex Interfaces User Guide for versions 25.1.1 and 25.3?
Description Due to a problem in the GTS Transceiver Dual Simplex Interfaces User Guide for the Quartus® Prime Pro Edition software version 25.1.1 and 25.3, there is not been updated properly. In the meantime, the additional changes to Dual Simplex (DS) implementation, which is not currently documented up to version 25.3, are as follows: Simplex JESD204B IP supports DS pairing with simplex SerialLite IV for both the Agilex™ 5 FPGA and Agilex™ 3 FPGA, and JESD204C IPs for only the Agilex™ 5 FPGA DS mode is supported for SDI, HDMI, and DisplayPort IPs for Agilex™ 3 FPGA Starting from the Quartus Prime Pro Edition software version 25.3, use the HSSI Support Logic Assignment Editor instead for DS implementation. HSSI Support Logic Assignment Editor combined and replaced the Dual Simplex (DS) Assignment Editor and Dynamic Reconfiguration (DR) Assignment Editor. Overall, the DS design flow remains similar to before, and you may continue relying on Chapter 4 of the GTS Transceiver Dual Simplex Interfaces User Guide until the next update. Resolution The document is scheduled to be updated in a future release of the Quartus® Prime Pro Edition software.Why do the HPS Synopsys DesignWare APB timers fail to initialize in Linux* during the early boot stage in the FPGA HPS Embedded Software 25.1.1 and earlier?
Description Due to an inadequate configuration in the Linux* device tree node for the HPS Synopsys DesignWare APB timers in Agilex® 3, Agilex® 5, and Agilex® 7 FPGA devices, the timers remain in reset and fail to initialize during the early driver probe stages in FPGA HPS Embedded Software 25.1.1 and earlier. This problem is observed even when the timers are enabled through CONFIG_DW_APB_TIMER=y and CONFIG_DW_APB_TIMER_OF=y and enabled in the device tree. The root cause is that the timer driver is not a regular platform driver and does not support the probe/defer mechanism. The device tree timer nodes use a clock manager-dependent clock (clocks = <&clkmgr ...>; clock-names = "timer"), but the clock manager is not ready when the driver probes during early boot. As a result, timer initialization fails and the timers are unavailable during early boot. Resolution To work around this problem in FPGA HPS Embedded Software 25.1.1 and earlier, modify the clock configuration in each HPS timer node (timer0 through timer3) in the Linux device tree. Remove the clock manager reference (clocks and clock-names) and add clock-freq = <100000000> (100 MHz L4_SP clock). The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3 (FPGA HPS Embedded Software). Reference device trees in linux-socfpga use clock-freq instead of clocks/clock-names from the clock manager.
