Why does the SEU test for Zephyr RTOS fail in the Agilex® 5 FPGA Premium development kit when using ATF and GHRD from the Quartus® Prime Pro Edition Software version 24.3.1 and later release?
Description Due to a compatibility problem between the latest version of Zephyr (24.3) and the ATF and GHRD releases from the Quartus® Prime Pro Edition Software version 24.3.1 and later, the SEU Zephyr test fails with a hang in the Agilex® 5 FPGA Premium Development kit. The test hangs after the following messages: SEU Test Started The Client No is 0x26ccad96 The Client No is 0x26dbf773 SEU Safe Error Insert Test Started. <hang is observed here> Resolution To work around this problem, it is recommended to use the latest version of the components in which this test passes, which corresponds to the Quartus® Prime Pro Edition Software version 24.3 release as documented on the following page: https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd_zephyr/ug-zgsrd-agx5e-premium/ This problem will be fixed in a future release.Why is there a random hexadecimal number in my TCL console?
Description Due to a problem in the Quartus® Prime Pro Edition Software, you may see a random hexadecimal number printed in the TCL console after running the set_instance_assignment command. Resolution It is safe to ignore this number. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.
Why the Agilex® 5 FPGA Hard Processor System CoreSight Trace is not working?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, when enabling the Agilex® 5 FPGA Hard Processor System Coresight Trace it is not functioning. Resolution To work around this problem, enable either one of the fabric debug feature such as APB or JTAG and tie off the signals if they are not used. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why do I get the error Internal Error "No Active Family" when trying to generate a programming JAM file via command line "quartus_pfg"
Description When trying to generate a JAM programing file (.jam) via the quartus_pfg command line from a Chain Description File (.cdf). quartus_pfg -c <file>.cdf <file>.jam You may get the following error message: Internal Error: Sub-system: PGMIO, File: /quartus/pgm/pgmio/pgmio_jam.cpp, Line: 2873 No Active Family Stack Trace: Quartus 0x3cce3e: PGMIO_JAM::jam2_filter(int, PGMIO_JTAG_UNI_ENGINE*, std::basic_ifstream >&, std::ostream&) + 0x582 (pgm_pgmio) Quartus 0x3d0a7a: PGMIO_JAM::jam2_create_file(int, PGMIO_JTAG_UNI_ENGINE*) + 0x846 (pgm_pgmio) Quartus 0x3d4ec2: PGMIO_JAM::create_output_file(std::vector >*, FIO_PATH const&, bool) + 0x3e8c (pgm_pgmio) This error may be due to an issue were the source programming files on the .cdf file not being valid. Resolution To work around this problem, verify your programing source file or files with the following command line: quartus_pfg -i <source>.sof This command will help you determine if your source file or files are valid and invalid and provide additional info on the issues with the invalid files for troubleshooting. Replace the invalid files with valid ones once identified. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why is data packet loss due to CRC error observed in Agilex® 5 and Agilex® 3 TSN XCVR SGMII 1G mode?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, when running the TSN - SGMII XCVR System for the Agilex® 5 FPGA E-Series Premium Development Kit, you may observe data packet loss in the TX direction for a 1G SGMII configuration with the TSN transceiver PHY. This issue is not seen with 10m,100m, and 2.5G configurations. Resolution To work around this problem, some changes in the software and hardware design files are required. Software Changes: 1. Change link.speed1000 parameter value from XGMAC_CONFIG_SS_1000_GMII to XGMAC_CONFIG_SS_2500_GMII in the following file. <user_path>/src/sw/agilex5_dk_a5e065bb32aes1-gsrd-rootfs/tmp/work-shared/agilex5_dk_a5e065bb32aes1/kernel-source/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c mac->link.speed10 = XGMAC_CONFIG_SS_10_MII; mac->link.speed100 = XGMAC_CONFIG_SS_100_MII; -mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII; +mac->link.speed1000 = XGMAC_CONFIG_SS_2500_GMII; mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII; Hardware Design Changes: 1. Replace the existing input with 2'b00 for the signals below in the file below: <user_path>/applications.fpga.soc.agilex5e-ed-tsn-config3/src/hw/ghrd_agilex5_top.v .phy_0_gmii8b_mac_speed_export (2'b00), ... .phy_0_xcvr_mode_export (2'b00), Additional Information There is no workaround currently, and there is no plan to fix this problem.Why does marginal degradation of 1.8V VIL I/O standard occur on Stratix® 10 FPGAs and Agilex® FPGAs family SDM I/O pins after long-term operation?
Description On all Stratix® 10 FPGA and Agilex® FPGA devices, when the board MSEL is set to JTAG but Quartus® Prime design software is configured to AS or AVST×8, and SDM I/O pins are left unconnected (NC), long-term operation may cause the 1.8V VIL on those SDM I/O pins to degrade below the datasheet specification of 0.5985V (0.35 × 1.71V). Refer to device datasheet under Single-Ended I/O Standards Specifications section for SDM IO I/O standard specification. The degradation can lead to configuration issues. Resolution Select AVST×16 as the configuration scheme in Quartus when using JTAG MSEL with all SDM I/O pins left unconnected. AVST×16 does not use any SDM I/O pins, preventing the degradation. Refer to Configuration User Guide for the steps to enable dual-purpose pins when setting AVSTx16 mode in Quartus. Starting in Quartus® Prime Pro edition software version 26.1, a note will be updated in the Configuration User Guide and the tooltips for the Configuration scheme category under Device and Pin Options in Quartus.Why is the eCPRI FPGA Example Design unable to support interworking function (IWF) in the Agilex® 5 FPGA device?
Description Due to a problem in the eCPRI FPGA IP version 3.0.2, you may find that the user has no option to generate an Example Design with the interworking functions (IWF) parameter enabled for the Agilex® 5 FPGA device. Resolution There is no workaround currently, and there is no plan to fix this problem.Why does the EMIF or HPS EMIF calibration fail when sharing the IO Bank with the MIPI D-PHY IP？
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, you may observe Fabric EMIF calibration failure or HPS EMIF calibration failure when the Fabric EMIF or HPS EMIF is sharing the same IO Bank with MIPI D-PHY IP. This problem does not impact the DDR4 and DDR5 HPS EMIF implementation that is sharing only the RZQ pin with the MIPI D-PHY IP. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1,Error-[XMRE] Cross-module reference resolution error ./../..//../../ed_sim_tb/ed_sim_tb.sv, 286
Description You may see the error message below from Synopsys VCS* and VCS MX when using the Agilex™ 3 FPGA and Agilex™ 5 FPGA MIPI D-PHY Design Example, and Link 0 is set to RX mode and Link 1 is set to TX mode. Error-[XMRE] Cross-module reference resolution error ./../..//../../ed_sim_tb/ed_sim_tb.sv, 286 Error found while trying to resolve cross-module reference. token 'ppi_tg'. Originating module 'ed_sim_tb', first module hit 'ed_sim_tb'. Source info: while ((ed_sim_tb.ed_sim.dut.tg.tg.dphy_ppi_tg_inst.tg.tg_inst.PPI_RTL.ppi_agents[0].ppi_tg.ppi_gen.tst_cnt !== 'b1)) #(20000.000000000000) ; Resolution To work around this problem, please regenerate the MIPI D-PHY IP design example with Link 0 set to TX mode and Link 1 set to RX mode.Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 BYTE_CONTROL(s)). Fix the errors described in the submessages, and then rerun the Fitter.
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and earlier, you may encounter the below fitter error when entering an odd number (1 or 3 or 5 or 7) in the 'Byte Locations' setting in the MIPI D-PHY IP GUI when designing with the Agilex® 3 FPGA or Agilex® 5 FPGA MIPI D-PHY IP. Error(175001): The Fitter cannot place 1 BYTE_CONTROL, which is within Generic Component dphy_dut_dphy. Info(14596): Information about the failing component(s): Info(175028): The BYTE_CONTROL name(s): dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|dphy_link[0].dphy_link_used.io_blk_inst|byte_in_link[0].byte_control_wrap_inst|byte_control_inst Error(16234): No legal location could be found out of 32 considered location(s). Reasons why each location could not be used are summarized below: Error(175006): There is no routing connectivity between the BYTE_CONTROL and the BYTE_CONTROL Error(175022): The BYTE_CONTROL could not be placed in any location to satisfy its connectivity requirements Info(175029): 16 locations affected Error(175006): There is no routing connectivity between the BYTE_CONTROL and destination BYTE Info(175027): Destination: BYTE dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|dphy_link[0].dphy_link_used.io_blk_inst|byte_in_link[0].byte_wrap_inst|byte_inst Error(175022): The BYTE_CONTROL could not be placed in any location to satisfy its connectivity requirements Info(175021): The destination BYTE was placed in location BYTE_X126_Y147_N106 Info(175029): 16 locations affected Resolution To work around this problem, generate the MIPI D-PHY Design Example with only even number (0 or 2 or 4 or 6) in the 'Byte Locations' setting in the MIPI D-PHY IP GUI. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.
